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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-03-20 16:32:07 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2017-05-21 01:50:49 +0200 |
| commit | cfa2eaa4cc268e9ed23c5a8635bb8125d985c94e (patch) | |
| tree | 9fece9ed51964e2f3c4abf7bd7c49d2ce641aec5 /src/southbridge | |
| parent | 3db82be764bea9796a46bed436765f1194a29a27 (diff) | |
| download | coreboot-cfa2eaa4cc268e9ed23c5a8635bb8125d985c94e.tar.xz | |
nb/intel/x4x: Make raminit less verbose with CONFIG_DEBUG_RAM_SETUP
Hides JEDEC steps using the RAM_SPEW macro.
Also hides a hexdump of SPDs.
Change-Id: Ie2b484cf1f1d296823df0473e852d9d07ca20246
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge')
0 files changed, 0 insertions, 0 deletions