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authorTristan Corrick <tristan@corrick.kiwi>2018-12-06 22:46:58 +1300
committerPatrick Georgi <pgeorgi@google.com>2018-12-28 12:22:35 +0000
commitd3f01b21fa7bf9bf115088ddc032aa1cd0000945 (patch)
tree38bffbac06c031deb871931c3393efc4f732a8c2 /src/southbridge
parentc54d52d67d89fbd31f0723468737c62d7f97442f (diff)
downloadcoreboot-d3f01b21fa7bf9bf115088ddc032aa1cd0000945.tar.xz
sb/intel/lynxpoint: Handle H81 only having 6 PCIe root ports
The H81 chipset is the only non-LP Lynx Point chipset with 6 PCIe root ports, all others have 8 [1]. The existing PCIe code assumed that all non-LP chipsets had 8 root ports, which meant that port 6 would not be considered the last root port on H81, so `root_port_commit_config()` would not run. Ultimately, while PCIe still worked on H81, all the root ports would remain enabled, even if disabled in the devicetree. Also, remove `PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_{MIN,MAX}`, as they are unused, and the MAX constant is incorrect. Interestingly, this fixes an issue where GRUB is unable to halt the system. Tested on an ASRock H81M-HDS. The root ports disabled in the devicetree do indeed end up disabled. [1] IntelĀ® 8 Series/C220 Series Chipset Family Platform Controller Hub (PCH) Datasheet, revision 003, document number 328904. Change-Id: If3ce217e8a4f4ea4e111e4525b03dbbfc63f92b0 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30077 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/lynxpoint/pch.c10
-rw-r--r--src/southbridge/intel/lynxpoint/pch.h1
-rw-r--r--src/southbridge/intel/lynxpoint/pcie.c17
3 files changed, 19 insertions, 9 deletions
diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c
index 6596aa2f5d..1fb6d7ad54 100644
--- a/src/southbridge/intel/lynxpoint/pch.c
+++ b/src/southbridge/intel/lynxpoint/pch.c
@@ -45,6 +45,16 @@ int pch_silicon_revision(void)
return pch_revision_id;
}
+int pch_silicon_id(void)
+{
+ static int pch_id = -1;
+
+ if (pch_id < 0)
+ pch_id = pci_read_config16(pch_get_lpc_device(), PCI_DEVICE_ID);
+
+ return pch_id;
+}
+
int pch_silicon_type(void)
{
static int pch_type = -1;
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index a28d703130..ee041d9dd2 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -141,6 +141,7 @@ struct rcba_config_instruction
#if !defined(__ASSEMBLER__)
void pch_config_rcba(const struct rcba_config_instruction *rcba_config);
int pch_silicon_revision(void);
+int pch_silicon_id(void);
int pch_silicon_type(void);
int pch_is_lp(void);
u16 get_pmbase(void);
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 70bfe18242..750b53395c 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -23,10 +23,7 @@
#include "pch.h"
#include <southbridge/intel/common/gpio.h>
-/* LynxPoint-LP has 6 root ports while non-LP has 8. */
#define MAX_NUM_ROOT_PORTS 8
-#define H_NUM_ROOT_PORTS MAX_NUM_ROOT_PORTS
-#define LP_NUM_ROOT_PORTS (MAX_NUM_ROOT_PORTS - 2)
struct root_port_config {
/* RPFN is a write-once register so keep a copy until it is written */
@@ -49,10 +46,10 @@ static struct root_port_config rpc;
static inline int max_root_ports(void)
{
- if (pch_is_lp())
- return LP_NUM_ROOT_PORTS;
- else
- return H_NUM_ROOT_PORTS;
+ if (pch_is_lp() || pch_silicon_id() == PCI_DEVICE_ID_INTEL_LPT_H81)
+ return 6;
+
+ return 8;
}
static inline int root_port_is_first(struct device *dev)
@@ -208,8 +205,10 @@ static void pcie_enable_clock_gating(void)
pci_update_config8(dev, 0xe1, 0x7f, 0x80);
}
if (rp == 5 && !rpc.ports[5]->enabled &&
- !rpc.ports[6]->enabled &&
- !rpc.ports[7]->enabled) {
+ (rpc.ports[6] == NULL ||
+ !rpc.ports[6]->enabled) &&
+ (rpc.ports[7] == NULL ||
+ !rpc.ports[7]->enabled)) {
pci_update_config8(dev, 0xe2, ~1, 1);
pci_update_config8(dev, 0xe1, 0x7f, 0x80);
}