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authorKyösti Mälkki <kyosti.malkki@gmail.com>2015-03-18 13:09:47 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2015-06-04 11:21:42 +0200
commitde271a8f0a9b5d910ee98eeea25f71d4e1536f73 (patch)
treecb3218dd2864940f229b2ec56c24b5cdbde7994d /src/southbridge
parent757c8b485bfb3389142d4c4cbafa3fb319cf4d3c (diff)
downloadcoreboot-de271a8f0a9b5d910ee98eeea25f71d4e1536f73.tar.xz
PCI subsystem: Drop parameter max from scan_bus
Change-Id: Ib33d3363c8d42fa54ac07c11a7ab2bc7ee4ae8bf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8539 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/amd8131/bridge.c12
-rw-r--r--src/southbridge/amd/amd8132/bridge.c13
2 files changed, 10 insertions, 15 deletions
diff --git a/src/southbridge/amd/amd8131/bridge.c b/src/southbridge/amd/amd8131/bridge.c
index e638fae74d..cb76980555 100644
--- a/src/southbridge/amd/amd8131/bridge.c
+++ b/src/southbridge/amd/amd8131/bridge.c
@@ -192,16 +192,15 @@ static void amd8131_pcix_tune_dev(device_t dev, void *ptr)
pci_write_config16(dev, cap + PCI_X_CMD, cmd);
}
}
-static unsigned int amd8131_scan_bus(struct bus *bus,
- unsigned min_devfn, unsigned max_devfn, unsigned int max)
+static void amd8131_scan_bus(struct bus *bus,
+ unsigned min_devfn, unsigned max_devfn)
{
struct amd8131_bus_info info;
struct bus *pbus;
unsigned pos;
-
/* Find the children on the bus */
- max = pci_scan_bus(bus, min_devfn, max_devfn, max);
+ pci_scan_bus(bus, min_devfn, max_devfn);
/* Find the revision of the 8131 */
info.rev = pci_read_config8(bus->dev, PCI_CLASS_REVISION);
@@ -243,13 +242,13 @@ static unsigned int amd8131_scan_bus(struct bus *bus,
pcix_misc &= ~(0x1f << 16);
pci_write_config32(bus->dev, 0x40, pcix_misc);
- return max;
+ return;
}
/* If we are in conventional PCI mode nothing more is necessary.
*/
if (PCI_X_SSTATUS_MFREQ(info.sstatus) == PCI_X_SSTATUS_CONVENTIONAL_PCI) {
- return max;
+ return;
}
@@ -264,7 +263,6 @@ static unsigned int amd8131_scan_bus(struct bus *bus,
bus_path(pbus));
pbus->disable_relaxed_ordering = 1;
}
- return max;
}
static unsigned int amd8131_scan_bridge(device_t dev, unsigned int max)
diff --git a/src/southbridge/amd/amd8132/bridge.c b/src/southbridge/amd/amd8132/bridge.c
index 2684e7c241..48d7c5168c 100644
--- a/src/southbridge/amd/amd8132/bridge.c
+++ b/src/southbridge/amd/amd8132/bridge.c
@@ -138,15 +138,14 @@ static void amd8132_pcix_tune_dev(device_t dev, void *ptr)
}
-static unsigned int amd8132_scan_bus(struct bus *bus,
- unsigned min_devfn, unsigned max_devfn, unsigned int max)
+static void amd8132_scan_bus(struct bus *bus,
+ unsigned min_devfn, unsigned max_devfn)
{
struct amd8132_bus_info info;
unsigned pos;
-
/* Find the children on the bus */
- max = pci_scan_bus(bus, min_devfn, max_devfn, max);
+ pci_scan_bus(bus, min_devfn, max_devfn);
/* Find the revision of the 8132 */
info.rev = pci_read_config8(bus->dev, PCI_CLASS_REVISION);
@@ -181,20 +180,18 @@ static unsigned int amd8132_scan_bus(struct bus *bus,
pcix_misc &= ~(0x1f << 16);
pci_write_config32(bus->dev, 0x40, pcix_misc);
- return max;
+ return;
}
#endif
/* If we are in conventional PCI mode nothing more is necessary.
*/
if (PCI_X_SSTATUS_MFREQ(info.sstatus) == PCI_X_SSTATUS_CONVENTIONAL_PCI) {
- return max;
+ return;
}
/* Tune the devices on the bus */
amd8132_walk_children(bus, amd8132_pcix_tune_dev, &info);
-
- return max;
}
static unsigned int amd8132_scan_bridge(device_t dev, unsigned int max)