summaryrefslogtreecommitdiff
path: root/src/southbridge
diff options
context:
space:
mode:
authorPatrick Rudolph <patrick.rudolph@9elements.com>2018-04-18 10:11:59 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-04-20 13:03:54 +0000
commite56189cfd1d90a2ca13650a9d21ff82cb79ccda8 (patch)
tree0da4c1fec6bdb725e4065d4d687364ae5c63104d /src/southbridge
parent6fcb9b00c8b7f820bb5ef81a83a24cd656654272 (diff)
downloadcoreboot-e56189cfd1d90a2ca13650a9d21ff82cb79ccda8.tar.xz
pci: Move inline PCI functions to pci_ops.h
Move inline function where they belong to. Fixes compilation on non x86 platforms. Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25720 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/bd82x6x/early_pch_common.c1
-rw-r--r--src/southbridge/intel/bd82x6x/finalize.c1
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c1
-rw-r--r--src/southbridge/intel/common/acpi_pirq_gen.c1
-rw-r--r--src/southbridge/intel/fsp_bd82x6x/finalize.c1
-rw-r--r--src/southbridge/intel/fsp_i89xx/finalize.c1
-rw-r--r--src/southbridge/intel/lynxpoint/finalize.c1
-rw-r--r--src/southbridge/intel/lynxpoint/lpc.c1
-rw-r--r--src/southbridge/intel/lynxpoint/pcie.c1
9 files changed, 9 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_pch_common.c b/src/southbridge/intel/bd82x6x/early_pch_common.c
index a41c2f3ee4..2ef47a2e46 100644
--- a/src/southbridge/intel/bd82x6x/early_pch_common.c
+++ b/src/southbridge/intel/bd82x6x/early_pch_common.c
@@ -18,6 +18,7 @@
#include <timestamp.h>
#include <cpu/x86/tsc.h>
#include <device/pci_def.h>
+#include <device/pci_ops.h>
#include "pch.h"
#include <arch/acpi.h>
#include <console/console.h>
diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c
index f5cd9cc274..9724f08d93 100644
--- a/src/southbridge/intel/bd82x6x/finalize.c
+++ b/src/southbridge/intel/bd82x6x/finalize.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/post_codes.h>
#include <cpu/x86/smm.h>
#include <southbridge/intel/common/rcba.h>
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index c57eeca769..8d125eb6d8 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -18,6 +18,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include <device/pci_ops.h>
#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
#include <pc80/i8259.h>
diff --git a/src/southbridge/intel/common/acpi_pirq_gen.c b/src/southbridge/intel/common/acpi_pirq_gen.c
index 3ff591c1e5..fc26d1aa95 100644
--- a/src/southbridge/intel/common/acpi_pirq_gen.c
+++ b/src/southbridge/intel/common/acpi_pirq_gen.c
@@ -17,6 +17,7 @@
#include <arch/io.h>
#include <console/console.h>
#include <device/pci_def.h>
+#include <device/pci_ops.h>
#include <string.h>
#include "acpi_pirq_gen.h"
diff --git a/src/southbridge/intel/fsp_bd82x6x/finalize.c b/src/southbridge/intel/fsp_bd82x6x/finalize.c
index 5b65fb0a0d..af2f4e1561 100644
--- a/src/southbridge/intel/fsp_bd82x6x/finalize.c
+++ b/src/southbridge/intel/fsp_bd82x6x/finalize.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/post_codes.h>
#include "pch.h"
#include <spi-generic.h>
diff --git a/src/southbridge/intel/fsp_i89xx/finalize.c b/src/southbridge/intel/fsp_i89xx/finalize.c
index 5b65fb0a0d..af2f4e1561 100644
--- a/src/southbridge/intel/fsp_i89xx/finalize.c
+++ b/src/southbridge/intel/fsp_i89xx/finalize.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/post_codes.h>
#include "pch.h"
#include <spi-generic.h>
diff --git a/src/southbridge/intel/lynxpoint/finalize.c b/src/southbridge/intel/lynxpoint/finalize.c
index e95872be3c..590a24513a 100644
--- a/src/southbridge/intel/lynxpoint/finalize.c
+++ b/src/southbridge/intel/lynxpoint/finalize.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/post_codes.h>
#include <spi-generic.h>
#include "me.h"
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 03a77d9b3e..2e3795040d 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -19,6 +19,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include <device/pci_ops.h>
#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
#include <pc80/i8259.h>
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 006bec2200..73c81b484f 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -19,6 +19,7 @@
#include <device/pci.h>
#include <device/pciexp.h>
#include <device/pci_ids.h>
+#include <device/pci_ops.h>
#include "pch.h"
#include <southbridge/intel/common/gpio.h>