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authorElyes HAOUAS <ehaouas@noos.fr>2019-01-05 09:58:39 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-01-07 10:32:06 +0000
commite7dd3ca40504272ede602fe868275c70f3a61ee8 (patch)
treec05597afabf23de75d4b0c9d687a681a2c9018d5 /src/southbridge
parent5493b4543d80e6cabe4ce60341f0a02f1711da66 (diff)
downloadcoreboot-e7dd3ca40504272ede602fe868275c70f3a61ee8.tar.xz
sb/intel/fsp_rangeley: Fix typo in GPIO Level
Change-Id: I83886820b8c1acceb2007b694361fe8c30c34f7f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: David Guckian
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/fsp_rangeley/acpi/soc.asl2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl
index b55bd92dd1..dde6796ed0 100644
--- a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl
+++ b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl
@@ -93,7 +93,7 @@ Scope(\)
GIO2, 8,
GIO3, 8,
Offset(0x0c), // GPIO Level
- GL00, 1,
+ GP00, 1,
GP01, 1,
GP02, 1,
GP0e, 1,