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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-04-06 09:38:38 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-04-09 14:43:57 +0000 |
| commit | eb00e8722b21da6362f53179d24512d2236f62da (patch) | |
| tree | a98f39ef9b82ef2f030a95766c0604d5e86349f4 /src/southbridge | |
| parent | 25d20d3332d76cbeda8c38a39ba9af2ef762d417 (diff) | |
| download | coreboot-eb00e8722b21da6362f53179d24512d2236f62da.tar.xz | |
sb/intel/i82801gx: Use 'const' to set pci_devfn_t statically
Change-Id: I4b33b42f41c7e34c5eab70edf2f12862816220d8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/i82801gx/bootblock.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/early_smbus.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index 9164c585f9..44a6846458 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -8,7 +8,7 @@ static void enable_spi_prefetch(void) { u8 reg8; - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); reg8 = pci_read_config8(dev, BIOS_CNTL); reg8 &= ~(3 << 2); diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c index 3a1369a34b..1c0130194c 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/i82801gx/early_smbus.c @@ -14,7 +14,7 @@ uintptr_t smbus_base(void) int smbus_enable_iobar(uintptr_t base) { /* Set the SMBus device statically. */ - pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); + const pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); /* Check to make sure we've got the right device. */ if (pci_read_config16(dev, 0x2) != 0x27da) |