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authorVladimir Serbinenko <phcoder@gmail.com>2015-05-29 16:33:49 +0200
committerVladimir Serbinenko <phcoder@gmail.com>2015-06-10 05:33:18 +0200
commitf34082c0e3a6333e2a4cfc8c7715ecef552ac5a1 (patch)
tree4c8b63e2fc2eb604ead05d19c25e1a0a798b9834 /src/southbridge
parentf099e1bcff48d7d83c258c866c84a6eb90621434 (diff)
downloadcoreboot-f34082c0e3a6333e2a4cfc8c7715ecef552ac5a1.tar.xz
fsp_model_206ax: Use common i945-ivy tseg SMM init.
Change-Id: Iac390b565d709b11bc7a6631b11315994b6e2c3c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10466 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/fsp_bd82x6x/pch.h5
-rw-r--r--src/southbridge/intel/fsp_bd82x6x/smi.c1
2 files changed, 1 insertions, 5 deletions
diff --git a/src/southbridge/intel/fsp_bd82x6x/pch.h b/src/southbridge/intel/fsp_bd82x6x/pch.h
index 10e536e87f..9e3b4da1e9 100644
--- a/src/southbridge/intel/fsp_bd82x6x/pch.h
+++ b/src/southbridge/intel/fsp_bd82x6x/pch.h
@@ -64,11 +64,6 @@ void intel_pch_finalize_smm(void);
#if !defined(__ASSEMBLER__) && !defined(__ROMCC__)
#if !defined(__PRE_RAM__) && !defined(__SMM__)
#include "chip.h"
-/* These helpers are for performing SMM relocation. */
-void southbridge_smm_init(void);
-void southbridge_trigger_smi(void);
-void southbridge_clear_smi_status(void);
-
int pch_silicon_revision(void);
int pch_silicon_type(void);
int pch_silicon_supported(int type, int rev);
diff --git a/src/southbridge/intel/fsp_bd82x6x/smi.c b/src/southbridge/intel/fsp_bd82x6x/smi.c
index 7151340965..2b4d4ec8fd 100644
--- a/src/southbridge/intel/fsp_bd82x6x/smi.c
+++ b/src/southbridge/intel/fsp_bd82x6x/smi.c
@@ -27,6 +27,7 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
#include <string.h>
+#include <cpu/intel/smm/gen1/smi.h>
#include "pch.h"
/* While we read PMBASE dynamically in case it changed, let's