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| author | Stefan Reinauer <stepan@coresystems.de> | 2008-12-13 20:51:34 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2008-12-13 20:51:34 +0000 |
| commit | 045c348cf3d700670b5780dd713c2e75436e5b4a (patch) | |
| tree | e471f52dd964c6839dc7f42d32514424ab4c81de /src/southbridge | |
| parent | 42f03e564726fbc85842f30022e4d7c074e8cccc (diff) | |
| download | coreboot-045c348cf3d700670b5780dd713c2e75436e5b4a.tar.xz | |
Move mainboard specific changes to the coreboot memory table into the
mainboard specific code. (And add a hook to allow other mainboards do
a similar thing if required)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3812 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/amd/rs690/rs690_cmn.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/southbridge/amd/rs690/rs690_cmn.c b/src/southbridge/amd/rs690/rs690_cmn.c index b714dc87c5..d50a48547c 100644 --- a/src/southbridge/amd/rs690/rs690_cmn.c +++ b/src/southbridge/amd/rs690/rs690_cmn.c @@ -307,6 +307,8 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) */ void rs690_set_tom(device_t nb_dev) { + extern unsigned long uma_memory_start; + /* set TOM */ pci_write_config32(nb_dev, 0x90, uma_memory_start); nbmc_write_index(nb_dev, 0x1e, uma_memory_start); |