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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-09-25 14:23:31 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-09-25 14:23:31 +0000 |
| commit | 370d979a93b1a63d1f8afc1ec2eb7cf54947ce35 (patch) | |
| tree | 938036d81b7d1a128d6d90c8d2d6a5bc4aa6287c /src/southbridge | |
| parent | bcabf2fa749f0690da982aaba52d9045f231c119 (diff) | |
| download | coreboot-370d979a93b1a63d1f8afc1ec2eb7cf54947ce35.tar.xz | |
Various USB Debug Port fixes (trivial).
- Drop unused DBGP_DEFAULT #defines on boards with chipsets where no
USB Debug Port support is implemented anyway (at the moment, at least):
- hp/dl145_g3
- hp/dl165_g6_fam10
- ICH7: Move unrelated code out of set_debug_port(). All ICH southbridges
with Debug Port hardcode the physical USB port used as Debug Port to 1.
In other words, this port is not user-configurable (as seems to be
the case on NVIDIA MCP55). For now we keep the 'port' parameter in order
to not change the API, this might be fixed differently later.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5842 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx_usb_debug.c | 20 |
1 files changed, 11 insertions, 9 deletions
diff --git a/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c b/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c index 3539ef81e5..4fa3cb7aed 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c +++ b/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <usbdebug.h> + // An arbitrary address for the BAR #define EHCI_BAR 0xFEF00000 // These could be read from DEBUG_BASE (0:1d.7 R 0x5A 16bit) @@ -26,22 +28,22 @@ #define EHCI_PORTSC 0x44 #define EHCI_DEBUG_OFFSET 0xA0 -#include <usbdebug.h> +/* Required for successful build, but currently empty. */ +void set_debug_port(unsigned int port) +{ + /* Not needed, the ICH* southbridges hardcode physical USB port 1. */ +} -void set_debug_port(unsigned port) +static void i82801gx_enable_usbdebug(unsigned int port) { u32 dbgctl; + pci_write_config32(PCI_DEV(0, 0x1d, 7), EHCI_BAR_INDEX, EHCI_BAR); + pci_write_config8(PCI_DEV(0, 0x1d, 7), 0x04, 0x2); // Memory Space Enable + printk(BIOS_DEBUG, "Enabling OWNER_CNT\n"); dbgctl = read32(EHCI_BAR + EHCI_DEBUG_OFFSET); dbgctl |= (1 << 30); write32(EHCI_BAR + EHCI_DEBUG_OFFSET, dbgctl); } -static void i82801gx_enable_usbdebug(unsigned port) -{ - pci_write_config32(PCI_DEV(0, 0x1d, 7), EHCI_BAR_INDEX, EHCI_BAR); - pci_write_config8(PCI_DEV(0, 0x1d, 7), 0x04, 0x2); // Memory Space Enable - set_debug_port(port); -} - |