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author | Duncan Laurie <dlaurie@google.com> | 2019-01-07 11:57:03 -0800 |
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committer | Duncan Laurie <dlaurie@chromium.org> | 2019-01-08 19:12:15 +0000 |
commit | 3da1b0d439f249a3e4a056ba24890688adb88d4d (patch) | |
tree | 0d74cd3cdff1b21d9c909e4a96b6c4b5986ce860 /src/southbridge | |
parent | b9499024c74b95cb43dfc3ea14fed7929122eb2d (diff) | |
download | coreboot-3da1b0d439f249a3e4a056ba24890688adb88d4d.tar.xz |
soc/intel/cannonlake: Fix chipset_power_state structure
This structure is declared as a static CAR_GLOBAL in the common
PMC library code and in the SOC specific code. Remove the SOC
specific version and instead get the chipset_power_state pointer
from the PMC library.
This fixes events that were recorded in chipset_power_state at
boot but were reading as all zero when it was time to parse the
structure when logging events to flash.
Change-Id: I67a4f724c0707d98766ad28abd8d0b66a5615745
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Diffstat (limited to 'src/southbridge')
0 files changed, 0 insertions, 0 deletions