diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2019-03-24 12:27:31 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-04-18 09:57:51 +0000 |
| commit | 45d4b17f5e05cd493f19e69900a38ac805eb63b5 (patch) | |
| tree | ad0a7cd24289d204e00209aca5ae24689a05a496 /src/southbridge | |
| parent | cbf27fd8998bf8125de8407b4e64ab726a738962 (diff) | |
| download | coreboot-45d4b17f5e05cd493f19e69900a38ac805eb63b5.tar.xz | |
nb/intel/sandybridge: Move southbridge code to bd82x6x
Move the southbridge code to bd82x6x folder similar to the lynxpoint
implementation.
Tested on Lenovo T520 (Intel Sandy Bridge).
Still boots to OS, no errors visible in dmesg.
Change-Id: I8afc9f966033f45823f5dfde279e0f66de165e93
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_pch.c | 34 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 1 |
2 files changed, 35 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 88436213a0..a50a159668 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -18,6 +18,9 @@ #include <arch/cbfs.h> #include <ip_checksum.h> #include <device/pci_def.h> +#include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/common/pmbase.h> + /* For DMI bar. */ #include <northbridge/intel/sandybridge/sandybridge.h> @@ -367,3 +370,34 @@ early_pch_init_native (void) init_dmi(); } + +static void pch_enable_bars(void) +{ + pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + + pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); + + pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80); + + pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); + + /* Enable GPIO functionality. */ + pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); +} + +static void pch_generic_setup(void) +{ + RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ + write_pmbase16(TCO1_CNT, 1 << 11); /* halt timer */ +} + +void early_pch_init(void) +{ + pch_enable_lpc(); + + pch_enable_bars(); + + pch_generic_setup(); + + setup_pch_gpios(&mainboard_gpio_map); +} diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 741996531f..21b603108a 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -76,6 +76,7 @@ void southbridge_configure_default_intmap(void); void southbridge_rcba_config(void); void mainboard_rcba_config(void); void early_pch_init_native(void); +void early_pch_init(void); struct southbridge_usb_port { |