sb/broadcom/bcm5785: Drop support

Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which platforms using this code lack.

Change-Id: I2305e0d9de0d4b1768e171f4c65d07306e7c3801
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

15 files changed, 0 insertions, 1226 deletions

diff --git a/src/southbridge/broadcom/bcm5785/Kconfig b/src/southbridge/broadcom/bcm5785/Kconfig
deleted file mode 100644
index 1ec4f8f692..0000000000
--- a/src/southbridge/broadcom/bcm5785/Kconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-config SOUTHBRIDGE_BROADCOM_BCM5785
-	bool
-
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-	default "southbridge/broadcom/bcm5785/bootblock.c"
-	depends on SOUTHBRIDGE_BROADCOM_BCM5785
diff --git a/src/southbridge/broadcom/bcm5785/Makefile.inc b/src/southbridge/broadcom/bcm5785/Makefile.inc
deleted file mode 100644
index 70fba1f218..0000000000
--- a/src/southbridge/broadcom/bcm5785/Makefile.inc
+++ /dev/null
@@ -1,11 +0,0 @@
-ifeq ($(CONFIG_SOUTHBRIDGE_BROADCOM_BCM5785),y)
-
-ramstage-y += bcm5785.c
-ramstage-y += usb.c
-ramstage-y += lpc.c
-ramstage-y += sb_pci_main.c
-ramstage-y += ide.c
-ramstage-y += sata.c
-ramstage-y += reset.c
-
-endif
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.c b/src/southbridge/broadcom/bcm5785/bcm5785.c
deleted file mode 100644
index ea77359257..0000000000
--- a/src/southbridge/broadcom/bcm5785/bcm5785.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 AMD
- * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <device/pci_ids.h>
-#include "bcm5785.h"
-
-void bcm5785_enable(struct device *dev)
-{
-	struct device *sb_pci_main_dev;
-	struct device *bus_dev;
-	// unsigned index;
-
-	/* See if we are on the behind the pcix bridge */
-	bus_dev = dev->bus->dev;
-	if ((bus_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
-		(bus_dev->device == 0x0036)) // device under PCI-X Bridge
-	{
-		unsigned int devfn;
-		devfn = bus_dev->path.pci.devfn + (1 << 3);
-		sb_pci_main_dev = pcidev_path_behind(bus_dev->bus, devfn);
-		// index = ((dev->path.pci.devfn & ~7) >> 3) + 8;
-	} else if ((bus_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
-		(bus_dev->device == 0x0104)) // device under PCI Bridge (under PCI-X)
-	{
-		unsigned int devfn;
-		devfn = bus_dev->bus->dev->path.pci.devfn + (1 << 3);
-		sb_pci_main_dev = pcidev_path_behind(bus_dev->bus->dev->bus,
-						devfn);
-		// index = ((dev->path.pci.devfn & ~7) >> 3) + 8;
-	}
-	else { // same bus
-		unsigned int devfn;
-		devfn = (dev->path.pci.devfn) & ~7;
-		if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS) {
-			if (dev->device == 0x0036) //PCI-X Bridge
-			{ devfn += (1<<3); }
-			else if (dev->device == 0x0223) // USB
-			{ devfn -= (1<<3); }
-		}
-		sb_pci_main_dev = pcidev_path_behind(dev->bus, devfn);
-		// index = dev->path.pci.devfn & 7;
-	}
-	if (!sb_pci_main_dev) {
-		return;
-	}
-
-	// get index now
-#if 0
-	unsigned int reg_old, reg;
-	if (index < 16) {
-		reg = reg_old = pci_read_config16(sb_pci_main_dev, 0x48);
-		reg &= ~(1 << index);
-		if (dev->enabled) {
-			reg |= (1 << index);
-		}
-		if (reg != reg_old) {
-			pci_write_config16(sb_pci_main_dev, 0x48, reg);
-		}
-	}
-	else if (index == 16) {
-		reg = reg_old = pci_read_config8(sb_pci_main_dev, 0x47);
-		reg &= ~(1 << 7);
-		if (!dev->enabled) {
-			reg |= (1 << 7);
-		}
-		if (reg != reg_old) {
-			pci_write_config8(sb_pci_main_dev, 0x47, reg);
-		}
-	}
-#endif
-}
-
-void bcm5785_set_subsystem(struct device *dev, unsigned int vendor,
-			       unsigned int device)
-{
-	pci_write_config32(dev, 0x40,
-		((device & 0xffff) << 16) | (vendor & 0xffff));
-}
-
-struct chip_operations southbridge_broadcom_bcm5785_ops = {
-	CHIP_NAME("Serverworks BCM5785 Southbridge")
-	.enable_dev = bcm5785_enable,
-};
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.h b/src/southbridge/broadcom/bcm5785/bcm5785.h
deleted file mode 100644
index db723dd8b3..0000000000
--- a/src/southbridge/broadcom/bcm5785/bcm5785.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 AMD
- * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef BCM5785_H
-#define BCM5785_H
-
-#include <device/device.h>
-#include "chip.h"
-
-void bcm5785_enable(struct device *dev);
-void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn);
-
-void bcm5785_set_subsystem(struct device *dev, unsigned int vendor,
-			       unsigned int device);
-
-void ldtstop_sb(void);
-
-#endif /* BCM5785_H */
diff --git a/src/southbridge/broadcom/bcm5785/bootblock.c b/src/southbridge/broadcom/bcm5785/bootblock.c
deleted file mode 100644
index c14f47aa53..0000000000
--- a/src/southbridge/broadcom/bcm5785/bootblock.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 AMD
- * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <device/pci_ops.h>
-#include <device/pci_ids.h>
-#include <device/pci_type.h>
-
-#define PCI_ID(VENDOR_ID, DEVICE_ID) \
-	((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
-
-static pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev)
-{
-	for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) {
-		unsigned int id;
-		id = pci_read_config32(dev, 0);
-		if (id == pci_id)
-			return dev;
-	}
-	return PCI_DEV_INVALID;
-}
-
-/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */
-static void bcm5785_enable_rom(void)
-{
-	u8 byte;
-	pci_devfn_t dev;
-
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SERVERWORKS,
-			PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN), 0);
-
-	/* Set the 4MB enable bits. */
-	byte = pci_read_config8(dev, 0x41);
-	byte |= 0x0e;
-	pci_write_config8(dev, 0x41, byte);
-}
-
-static void bootblock_southbridge_init(void)
-{
-	bcm5785_enable_rom();
-}
diff --git a/src/southbridge/broadcom/bcm5785/chip.h b/src/southbridge/broadcom/bcm5785/chip.h
deleted file mode 100644
index 2c6573439c..0000000000
--- a/src/southbridge/broadcom/bcm5785/chip.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 AMD
- * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef BCM5785_CHIP_H
-#define BCM5785_CHIP_H
-
-struct southbridge_broadcom_bcm5785_config
-{
-	unsigned int ide0_enable : 1;
-	unsigned int ide1_enable : 1;
-	unsigned int sata0_enable : 1;
-	unsigned int sata1_enable : 1;
-};
-
-#endif /* BCM5785_CHIP_H */
diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c
deleted file mode 100644
index b4d623b98c..0000000000
--- a/src/southbridge/broadcom/bcm5785/early_setup.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 AMD
- * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <device/pci_ops.h>
-#include <reset.h>
-#include <southbridge/amd/common/reset.h>
-#include "bcm5785.h"
-
-static void bcm5785_enable_lpc(void)
-{
-	uint8_t byte;
-	pci_devfn_t dev;
-
-	dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
-
-	/* LPC Control 0 */
-	byte = pci_read_config8(dev, 0x44);
-	/* Serial 0 */
-	byte |= 1 << 6;
-	pci_write_config8(dev, 0x44, byte);
-
-	/* LPC Control 4 */
-	byte = pci_read_config8(dev, 0x48);
-	/* superio port 0x2e/4e enable */
-	byte |= (1 << 1) | (1 << 0);
-	pci_write_config8(dev, 0x48, byte);
-}
-
-static void bcm5785_enable_wdt_port_cf9(void)
-{
-	pci_devfn_t dev;
-	uint32_t dword;
-	uint32_t dword_old;
-
-	dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
-
-	dword_old = pci_read_config32(dev, 0x4c);
-	dword = dword_old | (1 << 4); //enable Timer Func
-	if (dword != dword_old)
-		pci_write_config32(dev, 0x4c, dword);
-
-	dword_old = pci_read_config32(dev, 0x6c);
-	dword = dword_old | (1 << 9); //unhide Timer Func in pci space
-	if (dword != dword_old)
-		pci_write_config32(dev, 0x6c, dword);
-
-	dev = pci_locate_device(PCI_ID(0x1166, 0x0238), 0);
-
-	/* enable cf9 */
-	pci_write_config8(dev, 0x40, 1 << 2);
-}
-
-unsigned int get_sbdn(unsigned int bus)
-{
-	pci_devfn_t dev;
-
-	/* Find the device.
-	 * There can only be one bcm5785 on a hypertransport chain/bus.
-	 */
-	dev = pci_locate_device_on_bus(
-		PCI_ID(0x1166, 0x0036),
-		bus);
-
-	return (dev >> 15) & 0x1f;
-
-}
-
-#define SB_VFSMAF 0
-
-void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn)
-{
-	//ACPI Decode Enable
-	outb(0x0e, 0xcd6);
-	outb(1 << 3, 0xcd7);
-
-	// set port to 0x2060
-	outb(0x67, 0xcd6);
-	outb(0x60, 0xcd7);
-	outb(0x68, 0xcd6);
-	outb(0x20, 0xcd7);
-
-	outb(0x69, 0xcd6);
-	outb(7, 0xcd7);
-
-	outb(0x64, 0xcd6);
-	outb(9, 0xcd7);
-}
-
-void ldtstop_sb(void)
-{
-	outb(1, 0x2060);
-}
-
-
-void do_board_reset(void)
-{
-	bcm5785_enable_wdt_port_cf9();
-
-	set_bios_reset();
-
-	/* full reset */
-	outb(0x0a, 0x0cf9);
-	outb(0x0e, 0x0cf9);
-}
-
-void do_soft_reset(void)
-{
-	bcm5785_enable_wdt_port_cf9();
-
-	set_bios_reset();
-#if 1
-	/* link reset */
-//	outb(0x02, 0x0cf9);
-	outb(0x06, 0x0cf9);
-#endif
-}
-
-static void bcm5785_enable_msg(void)
-{
-	pci_devfn_t dev;
-	uint32_t dword;
-	uint32_t dword_old;
-	uint8_t byte;
-
-	dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
-
-	byte = pci_read_config8(dev, 0x42);
-	byte = 1 << 1; //enable a20
-	pci_write_config8(dev, 0x42, byte);
-
-	dword_old = pci_read_config32(dev, 0x6c);
-	// bit 5: enable A20 Message
-	// bit 4: enable interrupt messages
-	// bit 3: enable reset init message
-	// bit 2: enable keyboard init message
-	// bit 1: enable upsteam messages
-	// bit 0: enable shutdowm message to init generation
-
-	/* bit 1 and bit 4 must be set, otherwise
-	 * interrupt msg will not be delivered to the processor
-	 */
-	dword = dword_old | (1 << 5) | (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0);
-	if (dword != dword_old)
-		pci_write_config32(dev, 0x6c, dword);
-}
-
-static void bcm5785_early_setup(void)
-{
-	uint8_t byte;
-	uint32_t dword;
-	pci_devfn_t dev;
-
-//F0
-	// enable device on bcm5785 at first
-	dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
-	dword = pci_read_config32(dev, 0x64);
-	dword |= (1 << 15) | (1 << 11) | (1 << 3); // IOAPIC enable
-	dword |= 1 << 8; // USB enable
-	dword |= /* (1 << 27)|*/ 1 << 14; // IDE enable
-	pci_write_config32(dev, 0x64, dword);
-
-	byte = pci_read_config8(dev, 0x84);
-	byte |= 1 << 0; // SATA enable
-	pci_write_config8(dev, 0x84, byte);
-
-// WDT and cf9 for later in ramstage to call hard_reset
-	bcm5785_enable_wdt_port_cf9();
-
-	bcm5785_enable_msg();
-
-
-// IDE related
-	//F0
-	byte = pci_read_config8(dev, 0x4e);
-	byte |= 1 << 4; //enable IDE ext regs
-	pci_write_config8(dev, 0x4e, byte);
-
-	//F1
-	dev = pci_locate_device(PCI_ID(0x1166, 0x0214), 0);
-	byte = pci_read_config8(dev, 0x48);
-	byte &= ~1; // disable pri channel
-	pci_write_config8(dev, 0x48, byte);
-	pci_write_config8(dev, 0xb0, 0x01);
-	pci_write_config8(dev, 0xb2, 0x02);
-	byte = pci_read_config8(dev, 0x06);
-	byte |= 1 << 4; // so b0, b2 can not be changed from now
-	pci_write_config8(dev, 0x06, byte);
-	byte = pci_read_config8(dev, 0x49);
-	byte |= 1; // enable second channel
-	pci_write_config8(dev, 0x49, byte);
-
-	//F2
-	dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
-
-	byte = pci_read_config8(dev, 0x40);
-	byte |= (1 << 3) | (1 << 2); // LPC Retry, LPC to PCI DMA enable
-	pci_write_config8(dev, 0x40, byte);
-
-	pci_write_config32(dev, 0x60, 0x0000ffff); // LPC Memory hole start and end
-
-// USB related
-	pci_write_config8(dev, 0x90, 0x40);
-	pci_write_config8(dev, 0x92, 0x06);
-	pci_write_config8(dev, 0x9c, 0x7c); //PHY timinig register
-	pci_write_config8(dev, 0xa4, 0x02); //mask reg - low/full speed func
-	pci_write_config8(dev, 0xa5, 0x02); //mask reg - low/full speed func
-	pci_write_config8(dev, 0xa6, 0x00); //mask reg - high speed func
-	pci_write_config8(dev, 0xb4, 0x40);
-}
diff --git a/src/southbridge/broadcom/bcm5785/early_smbus.c b/src/southbridge/broadcom/bcm5785/early_smbus.c
deleted file mode 100644
index 05e401dae1..0000000000
--- a/src/southbridge/broadcom/bcm5785/early_smbus.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 AMD
- * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <console/console.h>
-#include <device/pci_ops.h>
-
-#include "smbus.h"
-
-#define SMBUS_IO_BASE 0x1000
-
-static void enable_smbus(void)
-{
-	pci_devfn_t dev;
-	dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); // 0x0201?
-
-	if (dev == PCI_DEV_INVALID) {
-		die("SMBUS controller not found\n");
-	}
-
-	printk(BIOS_DEBUG, "SMBus controller enabled\n");
-	/* set smbus iobase */
-	pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1);
-	/* Set smbus iospace enable */
-	pci_write_config8(dev, 0xd2, 0x03);
-	/* clear any lingering errors, so the transaction will run */
-	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
-}
-
-static inline int smbus_recv_byte(unsigned int device)
-{
-	return do_smbus_recv_byte(SMBUS_IO_BASE, device);
-}
-
-static inline int smbus_send_byte(unsigned int device, unsigned char val)
-{
-	return do_smbus_send_byte(SMBUS_IO_BASE, device, val);
-}
-
-static inline int smbus_read_byte(unsigned int device, unsigned int address)
-{
-	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
-}
-
-static inline int smbus_write_byte(unsigned int device, unsigned int address, unsigned char val)
-{
-	return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
-}
diff --git a/src/southbridge/broadcom/bcm5785/ide.c b/src/southbridge/broadcom/bcm5785/ide.c
deleted file mode 100644
index c143c22a53..0000000000
--- a/src/southbridge/broadcom/bcm5785/ide.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 AMD
- * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include "bcm5785.h"
-
-static void bcm5785_ide_read_resources(struct device *dev)
-{
-	/* Get the normal pci resources of this device */
-	pci_dev_read_resources(dev);
-
-	/* BAR */
-	pci_get_resource(dev, 0x64);
-
-	compact_resources(dev);
-}
-
-static void ide_init(struct device *dev)
-{
-}
-
-static struct pci_operations lops_pci = {
-	.set_subsystem = bcm5785_set_subsystem,
-};
-
-static struct device_operations ide_ops  = {
-	.read_resources   = bcm5785_ide_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init             = ide_init,
-	.scan_bus         = 0,
-//	.enable           = bcm5785_enable,
-	.ops_pci          = &lops_pci,
-};
-
-static const struct pci_driver ide_driver __pci_driver = {
-	.ops    = &ide_ops,
-	.vendor = PCI_VENDOR_ID_SERVERWORKS,
-	.device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_IDE,
-};
diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c
deleted file mode 100644
index 5ac15e0fd0..0000000000
--- a/src/southbridge/broadcom/bcm5785/lpc.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 AMD
- * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pnp.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <pc80/mc146818rtc.h>
-#include <pc80/isa-dma.h>
-#include <arch/ioapic.h>
-#include "bcm5785.h"
-
-static void lpc_init(struct device *dev)
-{
-	/* Initialize the real time clock */
-	cmos_init(0);
-
-	/* Initialize isa dma */
-	isa_dma_init();
-}
-
-static void bcm5785_lpc_read_resources(struct device *dev)
-{
-	struct resource *res;
-
-	/* Get the normal pci resources of this device */
-	pci_dev_read_resources(dev);
-
-	/* Add an extra subtractive resource for both memory and I/O. */
-	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->base = 0;
-	res->size = 0x1000;
-	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
-		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-
-	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->base = 0xff800000;
-	res->size = 0x00800000; /* 8 MB for flash */
-	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
-		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-
-	res = new_resource(dev, 3); /* IOAPIC */
-	res->base = IO_APIC_ADDR;
-	res->size = 0x00001000;
-	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-}
-
-/**
- * Enable resources for children devices.
- *
- * @param dev The device whos children's resources are to be enabled.
- */
-static void bcm5785_lpc_enable_childrens_resources(struct device *dev)
-{
-	struct bus *link;
-	uint32_t reg;
-
-	reg = pci_read_config8(dev, 0x44);
-
-	for (link = dev->link_list; link; link = link->next) {
-		struct device *child;
-		for (child = link->children; child; child = child->sibling) {
-			if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
-				struct resource *res;
-				for (res = child->resource_list; res; res = res->next) {
-					unsigned long base, end; // don't need long long
-					if (!(res->flags & IORESOURCE_IO)) continue;
-					base = res->base;
-					end = resource_end(res);
-					printk(BIOS_DEBUG, "bcm5785lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);
-					switch (base) {
-					case 0x60: //KBC
-					case 0x64:
-						reg |= (1<<29); break;
-					case 0x3f8: // COM1
-						reg |= (1<<6);	break;
-					case 0x2f8: // COM2
-						reg |= (1<<7);  break;
-					case 0x378: // Parallel 1
-						reg |= (1<<0); break;
-					case 0x3f0: // FD0
-						reg |= (1<<26); break;
-					case 0x220:  // Audio 0
-						reg |= (1<<14);	break;
-					case 0x300:  // MIDI 0
-						reg |= (1<<18);	break;
-					}
-				}
-			}
-		}
-	}
-	pci_write_config32(dev, 0x44, reg);
-
-
-}
-
-static void bcm5785_lpc_enable_resources(struct device *dev)
-{
-	pci_dev_enable_resources(dev);
-	bcm5785_lpc_enable_childrens_resources(dev);
-}
-
-static struct pci_operations lops_pci = {
-	.set_subsystem = bcm5785_set_subsystem,
-};
-
-static struct device_operations lpc_ops  = {
-	.read_resources   = bcm5785_lpc_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = bcm5785_lpc_enable_resources,
-	.init             = lpc_init,
-	.scan_bus         = scan_static_bus,
-//	.enable           = bcm5785_enable,
-	.ops_pci          = &lops_pci,
-};
-
-static const struct pci_driver lpc_driver __pci_driver = {
-	.ops    = &lpc_ops,
-	.vendor = PCI_VENDOR_ID_SERVERWORKS,
-	.device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_LPC,
-};
diff --git a/src/southbridge/broadcom/bcm5785/reset.c b/src/southbridge/broadcom/bcm5785/reset.c
deleted file mode 100644
index ad3ea8f5ba..0000000000
--- a/src/southbridge/broadcom/bcm5785/reset.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 AMD
- * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#define __SIMPLE_DEVICE__
-
-#include <arch/io.h>
-#include <reset.h>
-
-#include "../../../northbridge/amd/amdk8/reset_test.c"
-
-void do_board_reset(void)
-{
-	set_bios_reset();
-	/* Try rebooting through port 0xcf9 */
-	/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
-	outb((0 <<3)|(0<<2)|(1<<1), 0xcf9);
-	outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
-}
diff --git a/src/southbridge/broadcom/bcm5785/sata.c b/src/southbridge/broadcom/bcm5785/sata.c
deleted file mode 100644
index cdd4295531..0000000000
--- a/src/southbridge/broadcom/bcm5785/sata.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 AMD
- * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <delay.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <device/mmio.h>
-#include "bcm5785.h"
-
-static void sata_init(struct device *dev)
-{
-	uint8_t byte;
-
-	u8 *mmio;
-	struct resource *res;
-	u8 *mmio_base;
-	int i;
-
-	if (!(dev->path.pci.devfn & 7)) { // only set it in Func0
-		byte = pci_read_config8(dev, 0x78);
-		byte |= (1<<7);
-		pci_write_config8(dev, 0x78, byte);
-
-	        res = find_resource(dev, 0x24);
-		mmio_base = res2mmio(res, 0, 3);
-
-		write32(mmio_base + 0x10f0, 0x40000001);
-		write32(mmio_base + 0x8c, 0x00ff2007);
-		mdelay(10);
-		write32(mmio_base + 0x8c, 0x78592009);
-		mdelay(10);
-		write32(mmio_base + 0x8c, 0x00082004);
-		mdelay(10);
-		write32(mmio_base + 0x8c, 0x00002004);
-		mdelay(10);
-
-		//init PHY
-
-		printk(BIOS_DEBUG, "init PHY...\n");
-		for (i=0; i<4; i++) {
-			mmio = (u8 *)(uintptr_t)(res->base + 0x100 * i);
-			byte = read8(mmio + 0x40);
-			printk(BIOS_DEBUG, "port %d PHY status = %02x\n", i, byte);
-			if (byte & 0x4) {// bit 2 is set
-				byte = read8(mmio+0x48);
-				write8(mmio + 0x48, byte | 1);
-				write8(mmio + 0x48, byte & (~1));
-				byte = read8(mmio + 0x40);
-				printk(BIOS_DEBUG, "after reset port %d PHY status = %02x\n", i, byte);
-			}
-		}
-	}
-}
-
-static struct pci_operations lops_pci = {
-	.set_subsystem = bcm5785_set_subsystem,
-};
-
-static struct device_operations sata_ops  = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-//	.enable           = bcm5785_enable,
-	.init             = sata_init,
-	.scan_bus         = 0,
-	.ops_pci          = &lops_pci,
-};
-
-static const struct pci_driver sata0_driver __pci_driver = {
-	.ops    = &sata_ops,
-	.vendor = PCI_VENDOR_ID_SERVERWORKS,
-	.device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_SATA,
-};
diff --git a/src/southbridge/broadcom/bcm5785/sb_pci_main.c b/src/southbridge/broadcom/bcm5785/sb_pci_main.c
deleted file mode 100644
index 837ce42b4b..0000000000
--- a/src/southbridge/broadcom/bcm5785/sb_pci_main.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 AMD
- * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pnp.h>
-#include <device/pci_ids.h>
-#include <pc80/mc146818rtc.h>
-#include <pc80/isa-dma.h>
-#include <arch/io.h>
-#include <device/smbus.h>
-#include "bcm5785.h"
-#include "smbus.h"
-
-#define NMI_OFF 0
-
-static void sb_init(struct device *dev)
-{
-	uint8_t byte;
-	uint8_t byte_old;
-	int nmi_option;
-
-	/* Set up NMI on errors */
-	byte = inb(0x70); // RTC70
-	byte_old = byte;
-	nmi_option = NMI_OFF;
-	get_option(&nmi_option, "nmi");
-	if (nmi_option) {
-		byte &= ~(1 << 7); /* set NMI */
-	} else {
-		byte |= (1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
-	}
-	if (byte != byte_old) {
-		outb(byte, 0x70);
-	}
-
-
-}
-
-static void bcm5785_sb_read_resources(struct device *dev)
-{
-	struct resource *res;
-
-	/* Get the normal pci resources of this device */
-	pci_dev_read_resources(dev);
-	/* Get Resource for SMBUS */
-	pci_get_resource(dev, 0x90);
-
-	compact_resources(dev);
-
-	/* Add an extra subtractive resource for both memory and I/O */
-	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
-	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
-}
-
-static int lsmbus_recv_byte(struct device *dev)
-{
-	unsigned int device;
-	struct resource *res;
-	struct bus *pbus;
-
-	device = dev->path.i2c.device;
-	pbus = get_pbus_smbus(dev);
-
-	res = find_resource(pbus->dev, 0x90);
-
-	return do_smbus_recv_byte(res->base, device);
-}
-
-static int lsmbus_send_byte(struct device *dev, uint8_t val)
-{
-	unsigned int device;
-	struct resource *res;
-	struct bus *pbus;
-
-	device = dev->path.i2c.device;
-	pbus = get_pbus_smbus(dev);
-
-	res = find_resource(pbus->dev, 0x90);
-
-	return do_smbus_send_byte(res->base, device, val);
-}
-
-static int lsmbus_read_byte(struct device *dev, uint8_t address)
-{
-	unsigned int device;
-	struct resource *res;
-	struct bus *pbus;
-
-	device = dev->path.i2c.device;
-	pbus = get_pbus_smbus(dev);
-
-	res = find_resource(pbus->dev, 0x90);
-
-	return do_smbus_read_byte(res->base, device, address);
-}
-
-static int lsmbus_write_byte(struct device *dev, uint8_t address, uint8_t val)
-{
-	unsigned int device;
-	struct resource *res;
-	struct bus *pbus;
-
-	device = dev->path.i2c.device;
-	pbus = get_pbus_smbus(dev);
-
-	res = find_resource(pbus->dev, 0x90);
-
-	return do_smbus_write_byte(res->base, device, address, val);
-}
-
-static struct smbus_bus_operations lops_smbus_bus = {
-	.recv_byte  = lsmbus_recv_byte,
-	.send_byte  = lsmbus_send_byte,
-	.read_byte  = lsmbus_read_byte,
-	.write_byte = lsmbus_write_byte,
-};
-
-static struct pci_operations lops_pci = {
-	.set_subsystem = pci_dev_set_subsystem,
-};
-
-static struct device_operations sb_ops = {
-	.read_resources   = bcm5785_sb_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init             = sb_init,
-	.scan_bus         = scan_smbus,
-//        .enable           = bcm5785_enable,
-	.ops_pci          = &lops_pci,
-	.ops_smbus_bus    = &lops_smbus_bus,
-};
-
-static const struct pci_driver sb_driver __pci_driver = {
-	.ops    = &sb_ops,
-	.vendor = PCI_VENDOR_ID_SERVERWORKS,
-	.device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN,
-};
diff --git a/src/southbridge/broadcom/bcm5785/smbus.h b/src/southbridge/broadcom/bcm5785/smbus.h
deleted file mode 100644
index 40ed774b72..0000000000
--- a/src/southbridge/broadcom/bcm5785/smbus.h
+++ /dev/null
@@ -1,193 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 AMD
- * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <device/smbus_def.h>
-
-#define SMBHSTSTAT 0x0
-#define SMBSLVSTAT 0x1
-#define SMBHSTCTRL 0x2
-#define SMBHSTCMD  0x3
-#define SMBHSTADDR 0x4
-#define SMBHSTDAT0 0x5
-#define SMBHSTDAT1 0x6
-#define SMBHSTBLKDAT 0x7
-
-#define SMBSLVCTRL 0x8
-#define SMBSLVCMD_SHADOW 0x9
-#define SMBSLVEVT 0xa
-#define SMBSLVDAT 0xc
-
-
-/* Between 1-10 seconds, We should never timeout normally
- * Longer than this is just painful when a timeout condition occurs.
- */
-#define SMBUS_TIMEOUT (100*1000*10)
-
-static inline void smbus_delay(void)
-{
-	outb(0x80, 0x80);
-}
-
-static int smbus_wait_until_ready(unsigned int smbus_io_base)
-{
-	unsigned long loops;
-	loops = SMBUS_TIMEOUT;
-	do {
-		unsigned char val;
-		val = inb(smbus_io_base + SMBHSTSTAT);
-		val &= 0x1f;
-		if (val == 0) { // ready now
-			return 0;
-		}
-		outb(val, smbus_io_base + SMBHSTSTAT);
-	} while (--loops);
-	return -2; // time out
-}
-
-static int smbus_wait_until_done(unsigned int smbus_io_base)
-{
-	unsigned long loops;
-	loops = SMBUS_TIMEOUT;
-	do {
-		unsigned char val;
-
-		val = inb(smbus_io_base + SMBHSTSTAT);
-		val &= 0x1f; // mask off reserved bits
-		if (val & 0x1c) {
-			return -5; // error
-		}
-		if (val == 0x02) {
-			outb(val, smbus_io_base + SMBHSTSTAT); // clear status
-			return 0; //
-		}
-	} while (--loops);
-	return -3; // timeout
-}
-
-static int do_smbus_recv_byte(unsigned int smbus_io_base, unsigned int device)
-{
-	uint8_t byte;
-
-	if (smbus_wait_until_ready(smbus_io_base) < 0) {
-		return -2; // not ready
-	}
-
-	/* set the device I'm talking to */
-	outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR);
-
-	byte = inb(smbus_io_base + SMBHSTCTRL);
-	byte &= 0xe3; // Clear [4:2]
-	byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command
-	outb(byte, smbus_io_base + SMBHSTCTRL);
-
-	/* poll for transaction completion */
-	if (smbus_wait_until_done(smbus_io_base) < 0) {
-		return -3; // timeout or error
-	}
-
-	/* read results of transaction */
-	byte = inb(smbus_io_base + SMBHSTCMD);
-
-	return byte;
-}
-
-static int do_smbus_send_byte(unsigned int smbus_io_base, unsigned int device, unsigned char val)
-{
-	uint8_t byte;
-
-	if (smbus_wait_until_ready(smbus_io_base) < 0) {
-		return -2; // not ready
-	}
-
-	/* set the command... */
-	outb(val, smbus_io_base + SMBHSTCMD);
-
-	/* set the device I'm talking to */
-	outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR);
-
-	byte = inb(smbus_io_base + SMBHSTCTRL);
-	byte &= 0xe3; // Clear [4:2]
-	byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command
-	outb(byte, smbus_io_base + SMBHSTCTRL);
-
-	/* poll for transaction completion */
-	if (smbus_wait_until_done(smbus_io_base) < 0) {
-		return -3; // timeout or error
-	}
-
-	return 0;
-}
-
-static int do_smbus_read_byte(unsigned int smbus_io_base, unsigned int device, unsigned int address)
-{
-	uint8_t byte;
-
-	if (smbus_wait_until_ready(smbus_io_base) < 0) {
-		return -2; // not ready
-	}
-
-	/* set the command/address... */
-	outb(address & 0xff, smbus_io_base + SMBHSTCMD);
-
-	/* set the device I'm talking to */
-	outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR);
-
-	byte = inb(smbus_io_base + SMBHSTCTRL);
-	byte &= 0xe3; // Clear [4:2]
-	byte |= (1<<3) | (1<<6); // Byte data read/write command, start the command
-	outb(byte, smbus_io_base + SMBHSTCTRL);
-
-	/* poll for transaction completion */
-	if (smbus_wait_until_done(smbus_io_base) < 0) {
-		return -3; // timeout or error
-	}
-
-	/* read results of transaction */
-	byte = inb(smbus_io_base + SMBHSTDAT0);
-
-	return byte;
-}
-
-static int do_smbus_write_byte(unsigned int smbus_io_base, unsigned int device, unsigned int address, unsigned char val)
-{
-	uint8_t byte;
-
-	if (smbus_wait_until_ready(smbus_io_base) < 0) {
-		return -2; // not ready
-	}
-
-	/* set the command/address... */
-	outb(address & 0xff, smbus_io_base + SMBHSTCMD);
-
-	/* set the device I'm talking to */
-	outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR);
-
-	/* output value */
-	outb(val, smbus_io_base + SMBHSTDAT0);
-
-	byte = inb(smbus_io_base + SMBHSTCTRL);
-	byte &= 0xe3; // Clear [4:2]
-	byte |= (1<<3) | (1<<6); // Byte data read/write command, start the command
-	outb(byte, smbus_io_base + SMBHSTCTRL);
-
-	/* poll for transaction completion */
-	if (smbus_wait_until_done(smbus_io_base) < 0) {
-		return -3; // timeout or error
-	}
-
-	return 0;
-}
diff --git a/src/southbridge/broadcom/bcm5785/usb.c b/src/southbridge/broadcom/bcm5785/usb.c
deleted file mode 100644
index ef374ad482..0000000000
--- a/src/southbridge/broadcom/bcm5785/usb.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 AMD
- * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "bcm5785.h"
-
-static void usb_init(struct device *dev)
-{
-	uint32_t dword;
-
-	dword = pci_read_config32(dev, 0x04);
-	dword |= (1<<2)|(1<<1)|(1<<0);
-	pci_write_config32(dev, 0x04, dword);
-
-	pci_write_config8(dev, 0x41, 0x00); // Serversworks said
-
-}
-
-static struct pci_operations lops_pci = {
-	.set_subsystem = bcm5785_set_subsystem,
-};
-
-static struct device_operations usb_ops  = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init             = usb_init,
-//	.enable           = bcm5785_enable,
-	.scan_bus         = 0,
-	.ops_pci          = &lops_pci,
-};
-
-static const struct pci_driver usb_driver __pci_driver = {
-	.ops    = &usb_ops,
-	.vendor = PCI_VENDOR_ID_SERVERWORKS,
-	.device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_USB,
-};