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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-12-03 12:36:09 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-12-09 05:23:55 +0000
commit657d68bddc030e38bc19eb4eef07f59b5e5258e4 (patch)
tree90d064a1e09721ae2e9279117ecb71f8ede854eb /src/southbridge
parentdafc78bb8d6bda8bddb029168491365b333ce529 (diff)
downloadcoreboot-657d68bddc030e38bc19eb4eef07f59b5e5258e4.tar.xz
AGESA,binaryPI: Move PORT80 selection to C bootblock
Because the function is implemented in C, post_code() calls from cache_as_ram.S and other early assembly entry files may not currently work for cold boots. Assembly implementation needs to follow one day. This effectively removes PORT80 routing from boards with ROMCC_BOOTBLOCK. Change-Id: I71aa94b33bd6f65e243724810472a440e98e0750 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/agesa/hudson/bootblock.c5
-rw-r--r--src/southbridge/amd/pi/hudson/bootblock.c5
2 files changed, 10 insertions, 0 deletions
diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c
index 97e8803f48..6925393b06 100644
--- a/src/southbridge/amd/agesa/hudson/bootblock.c
+++ b/src/southbridge/amd/agesa/hudson/bootblock.c
@@ -77,6 +77,11 @@ void bootblock_soc_early_init(void)
hudson_lpc_decode();
enable_acpimmio_decode_pm24();
+ if (CONFIG(POST_DEVICE_PCI_PCIE))
+ hudson_pci_port80();
+ else if (CONFIG(POST_DEVICE_LPC))
+ hudson_lpc_port80();
+
dev = PCI_DEV(0, 0x14, 3);
data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
/* enable 0x2e/0x4e IO decoding for SuperIO */
diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c
index e9a9d337c4..ec8663dad1 100644
--- a/src/southbridge/amd/pi/hudson/bootblock.c
+++ b/src/southbridge/amd/pi/hudson/bootblock.c
@@ -79,6 +79,11 @@ void bootblock_soc_early_init(void)
else
enable_acpimmio_decode_pm04();
+ if (CONFIG(POST_DEVICE_PCI_PCIE))
+ hudson_pci_port80();
+ else if (CONFIG(POST_DEVICE_LPC))
+ hudson_lpc_port80();
+
dev = PCI_DEV(0, 0x14, 3);
data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
/* enable 0x2e/0x4e IO decoding for SuperIO */