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authorAngel Pons <th3fanbus@gmail.com>2020-06-21 15:00:30 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-06-25 12:51:28 +0000
commit75bc530aa5b0ae680bb58731ed0ad8ca2e444da7 (patch)
treee342a1b46ee418e50aa0fb7feabb240832e46644 /src/southbridge
parent01e38559c36e5ca9e1cf69c7a674bf10aa156dd9 (diff)
downloadcoreboot-75bc530aa5b0ae680bb58731ed0ad8ca2e444da7.tar.xz
sb/intel/i82801jx: Rename GNVS `PSVT` and `CRTT`
Most other Intel southbridges call those `TPSV` and `TCRT` instead. Change-Id: Id4c30cd53abc544b743eb80696bfafe45929208e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42644 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/i82801jx/acpi/globalnvs.asl4
-rw-r--r--src/southbridge/intel/i82801jx/nvs.h4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl
index 34c550c206..3b6115feb5 100644
--- a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl
+++ b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl
@@ -36,11 +36,11 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
/* Thermal policy */
Offset (0x14),
ACTT, 8, // 0x14 - active trip point
- PSVT, 8, // 0x15 - passive trip point
+ TPSV, 8, // 0x15 - passive trip point
TC1V, 8, // 0x16 - passive trip point TC1
TC2V, 8, // 0x17 - passive trip point TC2
TSPV, 8, // 0x18 - passive trip point TSP
- CRTT, 8, // 0x19 - critical trip point
+ TCRT, 8, // 0x19 - critical trip point
DTSE, 8, // 0x1a - Digital Thermal Sensor enable
DTS1, 8, // 0x1b - DT sensor 1
FLVL, 8, // 0x1c - current fan level
diff --git a/src/southbridge/intel/i82801jx/nvs.h b/src/southbridge/intel/i82801jx/nvs.h
index 8dd012f03d..6b697f224e 100644
--- a/src/southbridge/intel/i82801jx/nvs.h
+++ b/src/southbridge/intel/i82801jx/nvs.h
@@ -22,11 +22,11 @@ typedef struct {
u8 dckn; /* 0x13 - PCIe docking state */
/* Thermal policy */
u8 actt; /* 0x14 - active trip point */
- u8 psvt; /* 0x15 - passive trip point */
+ u8 tpsv; /* 0x15 - passive trip point */
u8 tc1v; /* 0x16 - passive trip point TC1 */
u8 tc2v; /* 0x17 - passive trip point TC2 */
u8 tspv; /* 0x18 - passive trip point TSP */
- u8 crtt; /* 0x19 - critical trip point */
+ u8 tcrt; /* 0x19 - critical trip point */
u8 dtse; /* 0x1a - Digital Thermal Sensor enable */
u8 dts1; /* 0x1b - DT sensor 1 */
u8 flvl; /* 0x1c - current fan level */