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authorMarc Jones <marc.jones@se-eng.com>2015-04-22 23:16:31 -0600
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-04-24 00:37:37 +0200
commit786879777a70cb82c94588e6d14c8fdd18ab4345 (patch)
treea3dea1ee11739a00b63ffead17d7cd29078a70b8 /src/southbridge
parentbe34797e4c2a5b74bb8fcbbe9e4301b471d185e5 (diff)
downloadcoreboot-786879777a70cb82c94588e6d14c8fdd18ab4345.tar.xz
fsp: Move fsp to fsp1_0
Prepare for FSP 1.1 integration by moving the FSP to a FSP 1.0 specific directory. See follow-on patches for sharing of common code. Change-Id: Ic58cb4074c65b91d119909132a012876d7ee7b74 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/9970 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/fsp_rangeley/romstage.c2
-rw-r--r--src/southbridge/intel/fsp_rangeley/romstage.h2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c
index e6b4f62d7e..9596c7c7ac 100644
--- a/src/southbridge/intel/fsp_rangeley/romstage.c
+++ b/src/southbridge/intel/fsp_rangeley/romstage.c
@@ -29,7 +29,7 @@
#include <pc80/mc146818rtc.h>
#include <cbmem.h>
#include <console/console.h>
-#include <drivers/intel/fsp/fsp_util.h>
+#include <drivers/intel/fsp1_0/fsp_util.h>
#include "northbridge/intel/fsp_rangeley/northbridge.h"
#include "southbridge/intel/fsp_rangeley/soc.h"
#include "southbridge/intel/fsp_rangeley/gpio.h"
diff --git a/src/southbridge/intel/fsp_rangeley/romstage.h b/src/southbridge/intel/fsp_rangeley/romstage.h
index 4afce5f821..a421953c61 100644
--- a/src/southbridge/intel/fsp_rangeley/romstage.h
+++ b/src/southbridge/intel/fsp_rangeley/romstage.h
@@ -27,7 +27,7 @@
#include <stdint.h>
#include <arch/cpu.h>
-#include <drivers/intel/fsp/fsp_util.h>
+#include <drivers/intel/fsp1_0/fsp_util.h>
void main(FSP_INFO_HEADER *fsp_info_header);
void early_mainboard_romstage_entry(void);