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| author | Vladimir Serbinenko <phcoder@gmail.com> | 2014-01-02 10:16:46 +0100 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2014-01-23 20:29:52 +0100 |
| commit | 786c0f5fca4735f4d4b8d680749f6ef8b6198a3f (patch) | |
| tree | d9beb30045a3e018340306bb0c3bb771a00f7013 /src/southbridge | |
| parent | 969f8617e9ff4e71a11a8fc4567e8c8de33585a0 (diff) | |
| download | coreboot-786c0f5fca4735f4d4b8d680749f6ef8b6198a3f.tar.xz | |
nehalem: Fix SMRAM register address
Change-Id: If6646853039d15d6ba0fcf2b9b9b0658004be6e6
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4787
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/ibexpeak/smi.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/southbridge/intel/ibexpeak/smi.c b/src/southbridge/intel/ibexpeak/smi.c index f8d15ec41c..981be3bf40 100644 --- a/src/southbridge/intel/ibexpeak/smi.c +++ b/src/southbridge/intel/ibexpeak/smi.c @@ -334,6 +334,7 @@ static int smm_handler_copied = 0; static void smm_install(void) { device_t dev = PCI_DEV(0, 0, 0); + device_t qpdev = PCI_DEV(QUICKPATH_BUS, 0, 1); u32 smm_base = 0xa0000; struct ied_header ied = { .signature = "INTEL RSVD", @@ -349,7 +350,7 @@ static void smm_install(void) smm_handler_copied = 1; /* enable the SMM memory window */ - pci_write_config8(dev, SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG); + pci_write_config8(qpdev, QPD0F1_SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG); #if CONFIG_SMM_TSEG smm_base = pci_read_config32(dev, TSEG) & ~1; @@ -371,7 +372,7 @@ static void smm_install(void) wbinvd(); /* close the SMM memory window and enable normal SMM */ - pci_write_config8(dev, SMRAM, G_SMRAME | C_BASE_SEG); + pci_write_config8(qpdev, QPD0F1_SMRAM, G_SMRAME | C_BASE_SEG); } void smm_init(void) @@ -398,7 +399,7 @@ void smm_lock(void) * make the SMM registers writable again. */ printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(PCI_DEV(0, 0, 0), SMRAM, + pci_write_config8(PCI_DEV(QUICKPATH_BUS, 0, 1), QPD0F1_SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); } |