diff options
author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-06-08 17:20:38 +0200 |
---|---|---|
committer | Nico Huber <nico.h@gmx.de> | 2018-06-09 16:30:37 +0000 |
commit | 7a5f77142f68edd03874015300e471eb80d03c45 (patch) | |
tree | 055decdf9c0c5de4ea6dfb3bc8af106c9207a640 /src/southbridge | |
parent | 91b7cb1b7ad35ff6ecc76be2641cf0bfe5c24f8e (diff) | |
download | coreboot-7a5f77142f68edd03874015300e471eb80d03c45.tar.xz |
sb/intel/lynxpoint: Get rid of device_t
Use of device_t has been abandoned in ramstage.
Change-Id: I064ff5e76dd95c1770cd24139195b2a5fff2d382
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge')
-rw-r--r-- | src/southbridge/intel/lynxpoint/lpc.c | 32 | ||||
-rw-r--r-- | src/southbridge/intel/lynxpoint/pci.c | 2 | ||||
-rw-r--r-- | src/southbridge/intel/lynxpoint/pcie.c | 25 | ||||
-rw-r--r-- | src/southbridge/intel/lynxpoint/sata.c | 5 | ||||
-rw-r--r-- | src/southbridge/intel/lynxpoint/watchdog.c | 2 |
5 files changed, 35 insertions, 31 deletions
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index d1d00c6257..9d686dedf1 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -109,9 +109,9 @@ static void pch_enable_serial_irqs(struct device *dev) * 0x80 - The PIRQ is not routed. */ -static void pch_pirq_init(device_t dev) +static void pch_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -151,7 +151,7 @@ static void pch_pirq_init(device_t dev) } } -static void pch_gpi_routing(device_t dev) +static void pch_gpi_routing(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -180,7 +180,7 @@ static void pch_gpi_routing(device_t dev) pci_write_config32(dev, GPIO_ROUT, reg32); } -static void pch_power_options(device_t dev) +static void pch_power_options(struct device *dev) { u8 reg8; u16 reg16; @@ -420,7 +420,7 @@ static void enable_hpet(struct device *const dev) reg32 = RCBA32(HPTC); } -static void enable_clock_gating(device_t dev) +static void enable_clock_gating(struct device *dev) { /* LynxPoint Mobile */ u32 reg32; @@ -445,7 +445,7 @@ static void enable_clock_gating(device_t dev) RCBA32_OR(0x38c0, 0x7); // SPI Dynamic } -static void enable_lp_clock_gating(device_t dev) +static void enable_lp_clock_gating(struct device *dev) { /* LynxPoint LP */ u32 reg32; @@ -595,7 +595,7 @@ static void lpc_init(struct device *dev) pch_fixups(dev); } -static void pch_lpc_add_mmio_resources(device_t dev) +static void pch_lpc_add_mmio_resources(struct device *dev) { u32 reg; struct resource *res; @@ -657,7 +657,8 @@ static inline int pch_io_range_in_default(u16 base, u16 size) * Note: this function assumes there is no overlap with the default LPC device's * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. */ -static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index) +static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size, + int index) { struct resource *res; @@ -670,7 +671,8 @@ static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index) res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index) +static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value, + int index) { /* * Check if the register is enabled. If so and the base exceeds the @@ -683,7 +685,7 @@ static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index) } } -static void pch_lpc_add_io_resources(device_t dev) +static void pch_lpc_add_io_resources(struct device *dev) { struct resource *res; config_t *config = dev->chip_info; @@ -708,7 +710,7 @@ static void pch_lpc_add_io_resources(device_t dev) pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC); } -static void pch_lpc_read_resources(device_t dev) +static void pch_lpc_read_resources(struct device *dev) { global_nvs_t *gnvs; @@ -727,7 +729,7 @@ static void pch_lpc_read_resources(device_t dev) memset(gnvs, 0, sizeof(global_nvs_t)); } -static void pch_lpc_enable(device_t dev) +static void pch_lpc_enable(struct device *dev) { /* Enable PCH Display Port */ RCBA16(DISPBDF) = 0x0010; @@ -736,7 +738,7 @@ static void pch_lpc_enable(device_t dev) pch_enable(dev); } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -747,7 +749,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -static void southbridge_inject_dsdt(device_t dev) +static void southbridge_inject_dsdt(struct device *dev) { global_nvs_t *gnvs; @@ -788,7 +790,7 @@ static void southbridge_inject_dsdt(device_t dev) } } -static unsigned long southbridge_write_acpi_tables(device_t device, +static unsigned long southbridge_write_acpi_tables(struct device *device, unsigned long start, struct acpi_rsdp *rsdp) { diff --git a/src/southbridge/intel/lynxpoint/pci.c b/src/southbridge/intel/lynxpoint/pci.c index e2e052b270..3c43210dd9 100644 --- a/src/southbridge/intel/lynxpoint/pci.c +++ b/src/southbridge/intel/lynxpoint/pci.c @@ -104,7 +104,7 @@ static void ich_pci_bus_enable_resources(struct device *dev) ich_pci_dev_enable_resources(dev); } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { /* NOTE: This is not the default position! */ if (!vendor || !device) { diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 73c81b484f..a7966f15e1 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -42,7 +42,7 @@ struct root_port_config { int coalesce; int gbe_port; int num_ports; - device_t ports[MAX_NUM_ROOT_PORTS]; + struct device *ports[MAX_NUM_ROOT_PORTS]; }; static struct root_port_config rpc; @@ -55,18 +55,18 @@ static inline int max_root_ports(void) return H_NUM_ROOT_PORTS; } -static inline int root_port_is_first(device_t dev) +static inline int root_port_is_first(struct device *dev) { return PCI_FUNC(dev->path.pci.devfn) == 0; } -static inline int root_port_is_last(device_t dev) +static inline int root_port_is_last(struct device *dev) { return PCI_FUNC(dev->path.pci.devfn) == (rpc.num_ports - 1); } /* Root ports are numbered 1..N in the documentation. */ -static inline int root_port_number(device_t dev) +static inline int root_port_number(struct device *dev) { return PCI_FUNC(dev->path.pci.devfn) + 1; } @@ -101,7 +101,7 @@ static void root_port_config_update_gbe_port(void) } } -static void root_port_init_config(device_t dev) +static void root_port_init_config(struct device *dev) { int rp; @@ -154,7 +154,7 @@ static void root_port_init_config(device_t dev) /* Update devicetree with new Root Port function number assignment */ static void pch_pcie_device_set_func(int index, int pci_func) { - device_t dev; + struct device *dev; unsigned new_devfn; dev = rpc.ports[index]; @@ -187,7 +187,7 @@ static void pcie_enable_clock_gating(void) enabled_ports = 0; for (i = 0; i < rpc.num_ports; i++) { - device_t dev; + struct device *dev; int rp; dev = rpc.ports[i]; @@ -275,7 +275,7 @@ static void root_port_commit_config(void) pcie_enable_clock_gating(); for (i = 0; i < rpc.num_ports; i++) { - device_t dev; + struct device *dev; u32 reg32; dev = rpc.ports[i]; @@ -328,7 +328,7 @@ static void root_port_commit_config(void) RCBA32(RPFN) = rpc.new_rpfn; } -static void root_port_mark_disable(device_t dev) +static void root_port_mark_disable(struct device *dev) { /* Mark device as disabled. */ dev->enabled = 0; @@ -336,7 +336,7 @@ static void root_port_mark_disable(device_t dev) rpc.new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn)); } -static void root_port_check_disable(device_t dev) +static void root_port_check_disable(struct device *dev) { int rp; int is_lp; @@ -695,7 +695,7 @@ static void pci_init(struct device *dev) pci_write_config16(dev, 0x1e, reg16); } -static void pch_pcie_enable(device_t dev) +static void pch_pcie_enable(struct device *dev) { /* Add this device to the root port config structure. */ root_port_init_config(dev); @@ -715,7 +715,8 @@ static void pch_pcie_enable(device_t dev) root_port_commit_config(); } -static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void pcie_set_subsystem(struct device *dev, unsigned vendor, + unsigned device) { /* NOTE: This is not the default position! */ if (!vendor || !device) { diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index c45579b045..30e8aa8732 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -301,7 +301,7 @@ static void sata_init(struct device *dev) pci_write_config32(dev, 0x300, reg32); } -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -322,7 +322,8 @@ static void sata_enable(device_t dev) pci_write_config16(dev, 0x90, map); } -static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, + unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/lynxpoint/watchdog.c b/src/southbridge/intel/lynxpoint/watchdog.c index 74f69b032b..9a867e413a 100644 --- a/src/southbridge/intel/lynxpoint/watchdog.c +++ b/src/southbridge/intel/lynxpoint/watchdog.c @@ -28,7 +28,7 @@ // void watchdog_off(void) { - device_t dev; + struct device *dev; unsigned long value, base; /* Turn off the ICH7 watchdog. */ |