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| author | Shaunak Saha <shaunak.saha@intel.com> | 2016-09-09 15:15:27 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-09-15 01:20:06 +0200 |
| commit | b59991949580f59dbf0907881c7ea70729262e9a (patch) | |
| tree | 546cde921f237ced83588e876da4f6ebcd550f85 /src/southbridge | |
| parent | 563de15b8a4aafad162352754975158222f8de6c (diff) | |
| download | coreboot-b59991949580f59dbf0907881c7ea70729262e9a.tar.xz | |
google/reef: Remove setting of GPIO_TIER1_SCI enable bit
This patch removes setting of gpio_tier1_sci_en from mainboard
smihandler code. Gpio_tier1_sci enable bit is set from gpio.asl
now.
BUG=chrome-os-partner:56483
TEST=System resumes from S3 on lidopen, powerbutton and USB wake.
Also from S0iX system is resuming for WIFI wake.
Change-Id: I26fd3fd9fcc83c988bcff1bda4da7a2e3da98ce6
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/16566
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/southbridge')
0 files changed, 0 insertions, 0 deletions