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| author | Tristan Corrick <tristan@corrick.kiwi> | 2018-12-06 22:47:21 +1300 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-12-07 11:33:09 +0000 |
| commit | baa4c07ed4146bf744f47cbb8569a7b91d84edfe (patch) | |
| tree | ae5296587af17ef55d0d2db6d42ea2276245acd9 /src/southbridge | |
| parent | 1dcd8dbf760cd7b324d3a20f9e5f1c36fa95b5eb (diff) | |
| download | coreboot-baa4c07ed4146bf744f47cbb8569a7b91d84edfe.tar.xz | |
sb/intel/lynxpoint/pcie.c: Fix a mistake in a comment
The code annotated by the comment is dealing with root port 7, so update
the comment to reflect that. It looks like the comment was copied from
the root port 3 case, but not updated.
Change-Id: I0e27e4453f4c3b2b1b9dffb0c89b71373c6b303e
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pcie.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index a7966f15e1..70bfe18242 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -395,7 +395,7 @@ static void root_port_check_disable(struct device *dev) case 7: if (is_lp) break; - /* Root Port 3 is disabled in config 11b (1x4 links). */ + /* Root Port 7 is disabled in config 11b (1x4 links). */ if (((rpc.strpfusecfg2 >> 14) & 0x3) == 0x3) { root_port_mark_disable(dev); return; |