diff options
| author | Jimmy Zhang <jimmzhang@nvidia.com> | 2014-08-07 16:31:15 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-26 00:26:48 +0100 |
| commit | bd2b59cf2bda89f5f01b0f1c58093944589a0a03 (patch) | |
| tree | b031781fb001911bba63a64c4cc086d7f10066fa /src/southbridge | |
| parent | 9a1691dabe0a13f17f58ecfab7a9c162011f5780 (diff) | |
| download | coreboot-bd2b59cf2bda89f5f01b0f1c58093944589a0a03.tar.xz | |
ryu: Update BCT to Max Frequency 924MHz
Replace previous 528MHz BCT. This BCT contains four entries as below:
0: Samsung
1: Hynix
2: Micron
3: (spare) 528MHz Micron
BUG=none
BRANCH=none
TEST=Built and tested on Micron LPDDR.
Change-Id: Ibe9e299ac1dd4cabd390b2e78bbec6c0f3a3871b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3fcb3e82998c88220e87118efff0595ba3572e38
Original-Change-Id: I49e18ca8dc69f2ce9ded71f4f55c02a8b91f92b2
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/211479
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: http://review.coreboot.org/8919
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge')
0 files changed, 0 insertions, 0 deletions