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authorKyösti Mälkki <kyosti.malkki@gmail.com>2014-10-20 07:13:48 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-10-22 15:07:19 +0200
commitbedd6aff10675f77f31431adecb9dab2970ab61f (patch)
treeeb10a82f30124a4198e22dd346b0e798bf66c798 /src/southbridge
parent88db14d788c768f1124eb4f9c8ddff3d150e6cb6 (diff)
downloadcoreboot-bedd6aff10675f77f31431adecb9dab2970ab61f.tar.xz
amd/torpedo amd/dinar: Sanitize agesawrapper header
Change-Id: I3badb18839773e38834de967a51c29a306975d20 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7152 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/cimx/sb700/gpio_oem.h45
-rw-r--r--src/southbridge/amd/cimx/sb900/gpio_oem.h46
2 files changed, 91 insertions, 0 deletions
diff --git a/src/southbridge/amd/cimx/sb700/gpio_oem.h b/src/southbridge/amd/cimx/sb700/gpio_oem.h
index bc05e2a5b9..7acd4f50b5 100644
--- a/src/southbridge/amd/cimx/sb700/gpio_oem.h
+++ b/src/southbridge/amd/cimx/sb700/gpio_oem.h
@@ -1,6 +1,51 @@
#ifndef _CIMX_SB_GPIO_OEM_H_
#define _CIMX_SB_GPIO_OEM_H_
+#define MMIO_NP_BIT BIT7
+
+/* Hudson-2 ACPI PmIO Space Define */
+#define SB_ACPI_BASE_ADDRESS 0x0400
+#define ACPI_MMIO_BASE 0xFED80000
+#define SB_CFG_BASE 0x000 // DWORD
+#define GPIO_BASE 0x100 // BYTE
+#define SMI_BASE 0x200 // DWORD
+#define PMIO_BASE 0x300 // DWORD
+#define PMIO2_BASE 0x400 // BYTE
+#define BIOS_RAM_BASE 0x500 // BYTE
+#define CMOS_RAM_BASE 0x600 // BYTE
+#define CMOS_BASE 0x700 // BYTE
+#define ASF_BASE 0x900 // DWORD
+#define SMBUS_BASE 0xA00 // DWORD
+#define WATCHDOG_BASE 0xB00 // ??
+#define HPET_BASE 0xC00 // DWORD
+#define IOMUX_BASE 0xD00 // BYTE
+#define MISC_BASE 0xE00
+#define SERIAL_DEBUG_BASE 0x1000
+#define GFX_DAC_BASE 0x1400
+#define CEC_BASE 0x1800
+#define XHCI_BASE 0x1C00
+#define ACPI_SMI_DATA_PORT 0xB1
+#define R_SB_ACPI_PM1_STATUS 0x00
+#define R_SB_ACPI_PM1_ENABLE 0x02
+#define R_SB_ACPI_PM_CONTROL 0x04
+#define R_SB_ACPI_EVENT_STATUS 0x20
+#define R_SB_ACPI_EVENT_ENABLE 0x24
+#define B_PWR_BTN_STATUS BIT8
+#define B_WAKEUP_STATUS BIT15
+#define B_SCI_EN BIT0
+#define SB_PM_INDEX_PORT 0xCD6
+#define SB_PM_DATA_PORT 0xCD7
+#define SB_PMIOA_REG24 0x24 // AcpiMmioEn
+#define MmioAddress( BaseAddr, Register ) \
+ ( (UINTN)BaseAddr + \
+ (UINTN)(Register) \
+ )
+#define Mmio32Ptr( BaseAddr, Register ) \
+ ( (volatile UINT32 *)MmioAddress( BaseAddr, Register ) )
+#define Mmio32( BaseAddr, Register ) \
+ *Mmio32Ptr( BaseAddr, Register )
+
+
#define SB_GPIO_REG01 1
#define SB_GPIO_REG02 2
#define SB_GPIO_REG15 15
diff --git a/src/southbridge/amd/cimx/sb900/gpio_oem.h b/src/southbridge/amd/cimx/sb900/gpio_oem.h
new file mode 100644
index 0000000000..7a61569992
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb900/gpio_oem.h
@@ -0,0 +1,46 @@
+#ifndef _GPIO_OEM_H_
+#define _GPIO_OEM_H_
+
+/* Hudson-2 ACPI PmIO Space Define */
+#define SB_ACPI_BASE_ADDRESS 0x0400
+#define ACPI_MMIO_BASE 0xFED80000
+#define SB_CFG_BASE 0x000 // DWORD
+#define GPIO_BASE 0x100 // BYTE
+#define SMI_BASE 0x200 // DWORD
+#define PMIO_BASE 0x300 // DWORD
+#define PMIO2_BASE 0x400 // BYTE
+#define BIOS_RAM_BASE 0x500 // BYTE
+#define CMOS_RAM_BASE 0x600 // BYTE
+#define CMOS_BASE 0x700 // BYTE
+#define ASF_BASE 0x900 // DWORD
+#define SMBUS_BASE 0xA00 // DWORD
+#define WATCHDOG_BASE 0xB00 // ??
+#define HPET_BASE 0xC00 // DWORD
+#define IOMUX_BASE 0xD00 // BYTE
+#define MISC_BASE 0xE00
+#define SERIAL_DEBUG_BASE 0x1000
+#define GFX_DAC_BASE 0x1400
+#define CEC_BASE 0x1800
+#define XHCI_BASE 0x1C00
+#define ACPI_SMI_DATA_PORT 0xB1
+#define R_SB_ACPI_PM1_STATUS 0x00
+#define R_SB_ACPI_PM1_ENABLE 0x02
+#define R_SB_ACPI_PM_CONTROL 0x04
+#define R_SB_ACPI_EVENT_STATUS 0x20
+#define R_SB_ACPI_EVENT_ENABLE 0x24
+#define B_PWR_BTN_STATUS BIT8
+#define B_WAKEUP_STATUS BIT15
+#define B_SCI_EN BIT0
+#define SB_PM_INDEX_PORT 0xCD6
+#define SB_PM_DATA_PORT 0xCD7
+#define SB_PMIOA_REG24 0x24 // AcpiMmioEn
+#define MmioAddress( BaseAddr, Register ) \
+ ( (UINTN)BaseAddr + \
+ (UINTN)(Register) \
+ )
+#define Mmio32Ptr( BaseAddr, Register ) \
+ ( (volatile UINT32 *)MmioAddress( BaseAddr, Register ) )
+#define Mmio32( BaseAddr, Register ) \
+ *Mmio32Ptr( BaseAddr, Register )
+
+#endif