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authorRonald G. Minnich <rminnich@gmail.com>2006-03-14 19:58:14 +0000
committerRonald G. Minnich <rminnich@gmail.com>2006-03-14 19:58:14 +0000
commitc994c973c654817f5e764615776b78b84cd21910 (patch)
tree37e35c7cd905ef9b5cacc8dbd76628c134e5f68c /src/southbridge
parentd96e098def3ed64be0b775d4a6c058821e33b5ef (diff)
downloadcoreboot-c994c973c654817f5e764615776b78b84cd21910.tar.xz
Fix for nehemiah
other fixes for gx2 ram init. support for sharplfg00l04 -- not working yet. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2197 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/cs5535/cs5535_early_setup.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/southbridge/amd/cs5535/cs5535_early_setup.c b/src/southbridge/amd/cs5535/cs5535_early_setup.c
index ae3b7df441..6c32498aa9 100644
--- a/src/southbridge/amd/cs5535/cs5535_early_setup.c
+++ b/src/southbridge/amd/cs5535/cs5535_early_setup.c
@@ -103,10 +103,15 @@ static int cs5535_early_setup(void)
print_debug("reboot from BIOS reset\n\r");
return;
}
+ print_debug("Setup idsel\r\n");
cs5535_setup_idsel();
+ print_debug("Setup iobase\r\n");
cs5535_setup_iobase();
+ print_debug("Setup gpio\r\n");
cs5535_setup_gpio();
+ print_debug("Setup cis_mode\r\n");
cs5535_setup_cis_mode();
+ print_debug("Setup smbus\r\n");
cs5535_enable_smbus();
//get_memory_speed();
dummy();