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authorArthur Heymans <arthur@aheymans.xyz>2019-10-03 08:54:35 +0200
committerArthur Heymans <arthur@aheymans.xyz>2019-10-06 10:15:05 +0000
commitcea4fd9bb059dab2a0c10b48b1c645807665eec2 (patch)
tree9fe8c27a8d6b88d1119a44907cd2e874f8be2f2a /src/southbridge
parent896a2430d81867be2782e32f42fb160064feac57 (diff)
downloadcoreboot-cea4fd9bb059dab2a0c10b48b1c645807665eec2.tar.xz
nb/intel/nehalem: Move romstage boilerplate to a common location
Move the mainboard_romstage_entry to a common location and provide mainboard specific callbacks. Change-Id: Ia827053617cead5d2cf8e9f06cb68c2cbb668ca9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/ibexpeak/pch.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index 556b9e0a0b..fbe88a5d7c 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -65,6 +65,7 @@ int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf);
void early_thermal_init(void);
void southbridge_configure_default_intmap(void);
void pch_setup_cir(int chipset_type);
+void mainboard_lpc_init(void);
enum current_lookup_idx {
IF1_F57 = 0,
@@ -84,9 +85,11 @@ struct southbridge_usb_port {
enum current_lookup_idx current;
int oc_pin;
};
+
void early_usb_init(const struct southbridge_usb_port *portmap);
#ifndef __ROMCC__
+extern const struct southbridge_usb_port mainboard_usb_ports[14];
#include <device/device.h>
void pch_enable(struct device *dev);
#endif