Clean up #ifs

Replace #if CONFIG_FOO==1 with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} +

Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} +

Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} +

Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} +

(and some manual changes to fix false positives)

Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1004
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martin@se-eng.com>

34 files changed, 45 insertions, 45 deletions

diff --git a/src/southbridge/amd/amd8111/acpi.c b/src/southbridge/amd/amd8111/acpi.c
index d5b1c1891c..df57a7e2af 100644
--- a/src/southbridge/amd/amd8111/acpi.c
+++ b/src/southbridge/amd/amd8111/acpi.c
@@ -89,7 +89,7 @@ static int lsmbus_block_write(device_t dev, uint8_t cmd, u8 bytes, const u8 *buf
 }
 
 
-#if CONFIG_GENERATE_ACPI_TABLES == 1
+#if CONFIG_GENERATE_ACPI_TABLES
 unsigned pm_base;
 #endif
 
@@ -162,7 +162,7 @@ static void acpi_init(struct device *dev)
 				(on*12)+(on>>1),(on&1)*5);
 	}
 
-#if CONFIG_GENERATE_ACPI_TABLES == 1
+#if CONFIG_GENERATE_ACPI_TABLES
 	pm_base = pci_read_config16(dev, 0x58) & 0xff00;
 	printk(BIOS_DEBUG, "pm_base: 0x%04x\n",pm_base);
 #endif
diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c
index 401c039165..ce7707bd07 100644
--- a/src/southbridge/amd/cimx/sb700/bootblock.c
+++ b/src/southbridge/amd/cimx/sb700/bootblock.c
@@ -22,7 +22,7 @@
 #include <arch/romcc_io.h>
 
 
-#if CONFIG_CONSOLE_POST == 1
+#if CONFIG_CONSOLE_POST
 
 /* Data */
 #define UART_RBR 0x00
diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c
index c899320c48..3f647c8847 100644
--- a/src/southbridge/amd/cimx/sb700/early.c
+++ b/src/southbridge/amd/cimx/sb700/early.c
@@ -31,7 +31,7 @@
 #include "smbus.h"
 
 
-#if CONFIG_RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
 /**
  * @brief Get SouthBridge device number
  * @param[in] bus target bus number
diff --git a/src/southbridge/amd/cimx/sb700/sb_cimx.h b/src/southbridge/amd/cimx/sb700/sb_cimx.h
index 632e4cdcd5..8e62048d2e 100644
--- a/src/southbridge/amd/cimx/sb700/sb_cimx.h
+++ b/src/southbridge/amd/cimx/sb700/sb_cimx.h
@@ -40,7 +40,7 @@ void sb_Late_Post(void);
 void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base);
 void sb7xx_51xx_disable_wideio(u8 wio_index);
 
-#if CONFIG_RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
 /**
  * @brief Get SouthBridge device number, called by finalize_node_setup()
  * @param[in] bus target bus number
diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
index 7dc752a6cb..22d7724890 100644
--- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
+++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
@@ -158,7 +158,7 @@ typedef union _PCI_ADDR {
 
 #include "vendorcode/amd/cimx/sb800/AMDSBLIB.h"
 
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
 #include "spi.h"
 #endif
 
diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c
index 2b7315559a..71fea672d5 100644
--- a/src/southbridge/amd/cimx/sb800/cfg.c
+++ b/src/southbridge/amd/cimx/sb800/cfg.c
@@ -26,7 +26,7 @@
 #include <arch/io.h>
 #include <arch/acpi.h>
 
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
 int acpi_get_sleep_type(void)
 {
 	u16 tmp = inw(PM1_CNT_BLK_ADDRESS);
@@ -75,7 +75,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config)
 	if (!sb_config)
 		return;
 
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
 	if (acpi_get_sleep_type() == 3)
 		sb_config->S3Resume = 1;
 #endif
diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c
index f692897dcc..c0f85330f5 100644
--- a/src/southbridge/amd/cimx/sb800/early.c
+++ b/src/southbridge/amd/cimx/sb800/early.c
@@ -30,7 +30,7 @@
 #include "cbmem.h"
 
 
-#if CONFIG_RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
 /**
  * @brief Get SouthBridge device number
  * @param[in] bus target bus number
@@ -82,7 +82,7 @@ void sb800_clk_output_48Mhz(void)
         *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */
 }
 
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
 int acpi_is_wakeup_early(void)
 {
 	return (acpi_get_sleep_type() == 3);
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index c69782bc62..0ce82b3307 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -161,7 +161,7 @@ static const struct pci_driver raid5_driver __pci_driver = {
 	.device = PCI_DEVICE_ID_ATI_SB800_SATA_RAID5,
 };
 
-#if CONFIG_USBDEBUG == 1
+#if CONFIG_USBDEBUG
 static void usb_set_resources(struct device *dev)
 {
 	struct resource *res;
@@ -480,7 +480,7 @@ static void sb800_enable(device_t dev)
 		/* call the CIMX entry at the last sb800 device,
 		 * so make sure the mainboard devicetree is complete
 		 */
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
 		if (acpi_slp_type != 3)
 			sb_Before_Pci_Init();
 		else
diff --git a/src/southbridge/amd/cimx/sb800/sb_cimx.h b/src/southbridge/amd/cimx/sb800/sb_cimx.h
index 5e510de519..9916c8139b 100644
--- a/src/southbridge/amd/cimx/sb800/sb_cimx.h
+++ b/src/southbridge/amd/cimx/sb800/sb_cimx.h
@@ -40,7 +40,7 @@ int acpi_is_wakeup_early(void);
  */
 void sb800_clk_output_48Mhz(void);
 
-#if CONFIG_RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
 /**
  * @brief Get SouthBridge device number, called by finalize_node_setup()
  * @param[in] bus target bus number
diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c
index e84743bc20..61c3c3e928 100644
--- a/src/southbridge/amd/cimx/sb900/bootblock.c
+++ b/src/southbridge/amd/cimx/sb900/bootblock.c
@@ -22,7 +22,7 @@
 #include <arch/romcc_io.h>
 
 
-#if CONFIG_CONSOLE_POST == 1
+#if CONFIG_CONSOLE_POST
 
 /* Data */
 #define UART_RBR 0x00
diff --git a/src/southbridge/amd/cs5530/vga.c b/src/southbridge/amd/cs5530/vga.c
index 4a26251084..56bea45ad5 100644
--- a/src/southbridge/amd/cs5530/vga.c
+++ b/src/southbridge/amd/cs5530/vga.c
@@ -41,7 +41,7 @@
 #include <cpu/amd/gx1def.h>
 #include <delay.h>
 
-#if CONFIG_GX1_VIDEO == 1
+#if CONFIG_GX1_VIDEO
 /*
  * Some register descriptions that are no listed in cpu/amd/gx1def.h
  */
@@ -397,7 +397,7 @@ static void cs5530_activate_video(u32 io_base, const struct video_mode *mode)
 	write32(io_base + CS5530_DISPLAY_CONFIG, val | 0x0020002F);
 }
 
-#if CONFIG_SPLASH_GRAPHIC == 1
+#if CONFIG_SPLASH_GRAPHIC
 
 /*
  * This bitmap file must provide:
diff --git a/src/southbridge/amd/rs690/ht.c b/src/southbridge/amd/rs690/ht.c
index 5d816e59f4..9eb47bbdc5 100644
--- a/src/southbridge/amd/rs690/ht.c
+++ b/src/southbridge/amd/rs690/ht.c
@@ -27,7 +27,7 @@
 
 static void ht_dev_set_resources(device_t dev)
 {
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
 	unsigned reg;
 	device_t k8_f1;
 	resource_t rbase, rend;
@@ -86,7 +86,7 @@ static void ht_dev_set_resources(device_t dev)
 
 static void ht_dev_read_resources(device_t dev)
 {
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
 	struct resource *res;
 
 	printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__);
@@ -95,7 +95,7 @@ static void ht_dev_read_resources(device_t dev)
 
 	pci_dev_read_resources(dev);
 
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
 	/* Add an MMCONFIG resource. */
 	res = new_resource(dev, 0x1C);
 	res->base = EXT_CONF_BASE_ADDRESS;
diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c
index 8adf1f6a75..0540823f16 100644
--- a/src/southbridge/amd/rs780/early_setup.c
+++ b/src/southbridge/amd/rs780/early_setup.c
@@ -101,7 +101,7 @@ static void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
 	}
 }
 /* family 10 only, for reg > 0xFF */
-#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1
+#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10
 static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev, u32 reg_pos, u32 mask,
 				  u32 val)
 {
diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c
index 29a63943bc..e8d4596adf 100644
--- a/src/southbridge/amd/rs780/gfx.c
+++ b/src/southbridge/amd/rs780/gfx.c
@@ -659,7 +659,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
 	pointer = (u32 *)&vgainfo;
 	for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4)
 	{
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
 		*GpuF0MMReg = 0x80000000 + uma_memory_size - 512 + i;
 #else
 		*GpuF0MMReg = 0x80000000 + 0x8000000 - 512 + i;
@@ -775,7 +775,7 @@ static void rs780_internal_gfx_enable(device_t dev)
 	device_t nb_dev = dev_find_slot(0, 0);
 	msr_t sysmem;
 
-#if (CONFIG_GFXUMA == 0)
+#if !CONFIG_GFXUMA
 	u32 FB_Start, FB_End;
 #endif
 
@@ -818,7 +818,7 @@ static void rs780_internal_gfx_enable(device_t dev)
 	set_nbmc_enable_bits(nb_dev, 0x25, 0xffffffff, 0x111f111f);
 	set_htiu_enable_bits(nb_dev, 0x37, 1<<24, 1<<24);
 
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
 	/* GFX_InitUMA. */
 	/* Copy CPU DDR Controller to NB MC. */
 	device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c
index 717aeab2c6..9b153aae1b 100644
--- a/src/southbridge/amd/rs780/rs780.c
+++ b/src/southbridge/amd/rs780/rs780.c
@@ -220,7 +220,7 @@ static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev)
 
 	/* Program Straps. */
 	romstrap2 = 1 << 26; // enables audio function
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
 	extern uint64_t uma_memory_size;
 	// bits 7-9: aperture size
 	// 0-7: 128mb, 256mb, 64mb, 32mb, 512mb, 1g, 2g, 4g
diff --git a/src/southbridge/amd/sb600/ide.c b/src/southbridge/amd/sb600/ide.c
index e38e83fdd7..3fa31eab30 100644
--- a/src/southbridge/amd/sb600/ide.c
+++ b/src/southbridge/amd/sb600/ide.c
@@ -45,7 +45,7 @@ static void ide_init(struct device *dev)
 	dword |= 1 << 2;
 	pci_write_config16(dev, 0x4, dword);
 
-#if CONFIG_PCI_ROM_RUN == 1
+#if CONFIG_PCI_ROM_RUN
 	pci_dev_init(dev);
 #endif
 
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index 2dc84d84bc..c890ad90d3 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -715,7 +715,7 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
 	return nvram_pos;
 }
 
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
 int acpi_is_wakeup_early(void)
 {
 	u16 tmp;
diff --git a/src/southbridge/amd/sb700/ide.c b/src/southbridge/amd/sb700/ide.c
index 5f415fb9f2..19d4ed5d6a 100644
--- a/src/southbridge/amd/sb700/ide.c
+++ b/src/southbridge/amd/sb700/ide.c
@@ -60,7 +60,7 @@ static void ide_init(struct device *dev)
 		pci_write_config8(sm_dev, 0xAD, byte);
 	}
 
-#if CONFIG_PCI_ROM_RUN == 1
+#if CONFIG_PCI_ROM_RUN
 	pci_dev_init(dev);
 #endif
 }
diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c
index 5dd7d696aa..c968927854 100644
--- a/src/southbridge/amd/sb700/lpc.c
+++ b/src/southbridge/amd/sb700/lpc.c
@@ -73,7 +73,7 @@ static void lpc_init(device_t dev)
 
 	/* hack, but the whole sb700 startup lacks any device which
 	   is doing the acpi init */
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
 	{
 	extern u8 acpi_slp_type;
 	u16 tmp = inw(ACPI_PM1_CNT_BLK);
diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h
index 165c72d52b..d358ee8054 100644
--- a/src/southbridge/amd/sb700/sb700.h
+++ b/src/southbridge/amd/sb700/sb700.h
@@ -75,7 +75,7 @@ void sb7xx_51xx_setup_sata_phys(struct device *dev);
 
 #endif
 
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
 int acpi_is_wakeup_early(void);
 #endif
 
diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c
index 50f4ff70cd..a85f4902ca 100644
--- a/src/southbridge/amd/sb800/early_setup.c
+++ b/src/southbridge/amd/sb800/early_setup.c
@@ -665,7 +665,7 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
 	return nvram_pos;
 }
 
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
 static int acpi_is_wakeup_early(void)
 {
 	u16 tmp;
diff --git a/src/southbridge/amd/sb800/ide.c b/src/southbridge/amd/sb800/ide.c
index eb287f2cb2..a63878b41d 100644
--- a/src/southbridge/amd/sb800/ide.c
+++ b/src/southbridge/amd/sb800/ide.c
@@ -58,7 +58,7 @@ static void ide_init(struct device *dev)
 		pci_write_config8(dev, 0xAD, byte);
 	}
 
-#if CONFIG_PCI_ROM_RUN == 1
+#if CONFIG_PCI_ROM_RUN
 	pci_dev_init(dev);
 #endif
 }
diff --git a/src/southbridge/broadcom/bcm5780/nic.c b/src/southbridge/broadcom/bcm5780/nic.c
index 387c402215..0fa9a4e0d5 100644
--- a/src/southbridge/broadcom/bcm5780/nic.c
+++ b/src/southbridge/broadcom/bcm5780/nic.c
@@ -26,7 +26,7 @@
 
 static void nic_init(struct device *dev)
 {
-#if CONFIG_PCI_ROM_RUN == 1
+#if CONFIG_PCI_ROM_RUN
 	pci_dev_init(dev);// it will init option rom
 #endif
 
diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c
index 65af02abb0..b4d949376c 100644
--- a/src/southbridge/intel/i82371eb/smbus.c
+++ b/src/southbridge/intel/i82371eb/smbus.c
@@ -31,7 +31,7 @@
 #include "i82371eb.h"
 #include "smbus.h"
 
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
 extern u8 acpi_slp_type;
 int acpi_get_sleep_type(void);
 #endif
@@ -92,7 +92,7 @@ static void pwrmgt_enable(struct device *dev)
 	outw(0xffff,     DEFAULT_PMBASE + GLBSTS);
 	outl(0xffffffff, DEFAULT_PMBASE + DEVSTS);
 
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
 	/* this reads PMCNTRL, so we have to call it before writing the
 	 * default value */
 	acpi_slp_type = acpi_get_sleep_type();
diff --git a/src/southbridge/nvidia/ck804/early_setup.c b/src/southbridge/nvidia/ck804/early_setup.c
index dfe9ff2233..505d059c05 100644
--- a/src/southbridge/nvidia/ck804/early_setup.c
+++ b/src/southbridge/nvidia/ck804/early_setup.c
@@ -82,7 +82,7 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control,
 #define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
 #endif
 
-#if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
+#if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 #define CK804B_DEVN_BASE 1
 #else
 #define CK804B_DEVN_BASE CK804_DEVN_BASE
diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c
index bb0fd13d18..efe1b99ce4 100644
--- a/src/southbridge/nvidia/ck804/early_setup_car.c
+++ b/src/southbridge/nvidia/ck804/early_setup_car.c
@@ -72,7 +72,7 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control,
 #define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
 #endif
 
-#if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
+#if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 #define CK804B_DEVN_BASE 1
 #else
 #define CK804B_DEVN_BASE CK804_DEVN_BASE
diff --git a/src/southbridge/nvidia/ck804/ide.c b/src/southbridge/nvidia/ck804/ide.c
index ac94acbbed..c7236ec635 100644
--- a/src/southbridge/nvidia/ck804/ide.c
+++ b/src/southbridge/nvidia/ck804/ide.c
@@ -60,7 +60,7 @@ static void ide_init(struct device *dev)
 	dword |= 12;
 	pci_write_config32(dev, 0xf8, dword);
 
-#if CONFIG_PCI_ROM_RUN == 1
+#if CONFIG_PCI_ROM_RUN
 	pci_dev_init(dev);
 #endif
 }
diff --git a/src/southbridge/nvidia/ck804/nic.c b/src/southbridge/nvidia/ck804/nic.c
index ca6cd94caa..c62728addd 100644
--- a/src/southbridge/nvidia/ck804/nic.c
+++ b/src/southbridge/nvidia/ck804/nic.c
@@ -108,7 +108,7 @@ static void nic_init(struct device *dev)
 
 	nic_index++;
 
-#if CONFIG_PCI_ROM_RUN == 1
+#if CONFIG_PCI_ROM_RUN
 	pci_dev_init(dev);	/* It will init Option ROM. */
 #endif
 }
diff --git a/src/southbridge/nvidia/mcp55/ide.c b/src/southbridge/nvidia/mcp55/ide.c
index 0677a75f58..6d0cebf193 100644
--- a/src/southbridge/nvidia/mcp55/ide.c
+++ b/src/southbridge/nvidia/mcp55/ide.c
@@ -61,7 +61,7 @@ static void ide_init(struct device *dev)
 	dword = pci_read_config32(dev, 0xf8);
 	dword |= 12;
 	pci_write_config32(dev, 0xf8, dword);
-#if CONFIG_PCI_ROM_RUN == 1
+#if CONFIG_PCI_ROM_RUN
 	pci_dev_init(dev);
 #endif
 }
diff --git a/src/southbridge/nvidia/mcp55/nic.c b/src/southbridge/nvidia/mcp55/nic.c
index d74f10d247..0521b891aa 100644
--- a/src/southbridge/nvidia/mcp55/nic.c
+++ b/src/southbridge/nvidia/mcp55/nic.c
@@ -180,7 +180,7 @@ static void nic_init(struct device *dev)
 
 	nic_index++;
 
-#if CONFIG_PCI_ROM_RUN == 1
+#if CONFIG_PCI_ROM_RUN
 	pci_dev_init(dev);// it will init option rom
 #endif
 
diff --git a/src/southbridge/nvidia/mcp55/smbus.c b/src/southbridge/nvidia/mcp55/smbus.c
index 3b11dd3633..a945f237d0 100644
--- a/src/southbridge/nvidia/mcp55/smbus.c
+++ b/src/southbridge/nvidia/mcp55/smbus.c
@@ -94,7 +94,7 @@ static struct smbus_bus_operations lops_smbus_bus = {
 	.write_byte	= lsmbus_write_byte,
 };
 
-#if CONFIG_GENERATE_ACPI_TABLES == 1
+#if CONFIG_GENERATE_ACPI_TABLES
 unsigned pm_base;
 #endif
 
@@ -113,7 +113,7 @@ static void mcp55_sm_read_resources(device_t dev)
 
 static void mcp55_sm_init(device_t dev)
 {
-#if CONFIG_GENERATE_ACPI_TABLES == 1
+#if CONFIG_GENERATE_ACPI_TABLES
 	struct resource *res;
 
 	res = find_resource(dev, 0x60);
diff --git a/src/southbridge/sis/sis966/ide.c b/src/southbridge/sis/sis966/ide.c
index 90ea002a5a..d067b5c77a 100644
--- a/src/southbridge/sis/sis966/ide.c
+++ b/src/southbridge/sis/sis966/ide.c
@@ -144,7 +144,7 @@ print_debug("IDE_INIT:---------->\n");
 	dword = pci_read_config32(dev, 0xf8);
 	dword |= 12;
 	pci_write_config32(dev, 0xf8, dword);
-#if CONFIG_PCI_ROM_RUN == 1
+#if CONFIG_PCI_ROM_RUN
 	pci_dev_init(dev);
 #endif
 
diff --git a/src/southbridge/via/vt8237r/early_smbus.c b/src/southbridge/via/vt8237r/early_smbus.c
index e25535bf0f..0c820c03c2 100644
--- a/src/southbridge/via/vt8237r/early_smbus.c
+++ b/src/southbridge/via/vt8237r/early_smbus.c
@@ -327,7 +327,7 @@ void enable_rom_decode(void)
 	pci_write_config8(dev, 0x41, 0x7f);
 }
 
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
 static int acpi_is_wakeup_early(void) {
 	device_t dev;
 	u16 tmp;
diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index 7fc5b524fd..a47ab38a56 100644
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -244,7 +244,7 @@ static void setup_pm(device_t dev)
 
 	/* SCI is generated for RTC/pwrBtn/slpBtn. */
 	tmp = inw(VT8237R_ACPI_IO_BASE + 0x04);
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
 	acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
 	printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type);
 #endif