src: Get rid of duplicated includes

Change-Id: I252a1cd77bf647477edb7dddadb7e527de872439
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

15 files changed, 9 insertions, 28 deletions

diff --git a/src/southbridge/amd/cimx/sb900/SbPlatform.h b/src/southbridge/amd/cimx/sb900/SbPlatform.h
index 578c812ac3..660553fbd8 100644
--- a/src/southbridge/amd/cimx/sb900/SbPlatform.h
+++ b/src/southbridge/amd/cimx/sb900/SbPlatform.h
@@ -56,7 +56,6 @@ typedef union _PCI_ADDR {
 #include "SbType.h"
 #include "AcpiLib.h"
 #include "SbDef.h"
-#include "AmdSbLib.h"
 #include "SbSubFun.h"
 #include "platform_cfg.h"	/* mainboard specific configuration */
 #include <OEM.h>		/* platform default configuration */
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index f1f47d50cf..7ae538ebd2 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -32,7 +32,6 @@
 #include <cpu/x86/smm.h>
 #include <cbmem.h>
 #include <string.h>
-#include <cpu/x86/smm.h>
 #include "pch.h"
 #include "nvs.h"
 #include <southbridge/intel/common/pciehp.h>
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index da1c7e4d6e..1bbce066bf 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -32,11 +32,9 @@
 #include <elog.h>
 #include <halt.h>
 
-#ifdef __SMM__
-#include <arch/io.h>
-#else
-# include <device/device.h>
-# include <device/pci.h>
+#ifndef __SMM__
+#include <device/device.h>
+#include <device/pci.h>
 #endif
 
 #include "me.h"
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index 1a59dc4024..dc78e7184f 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -32,11 +32,9 @@
 #include <elog.h>
 #include <halt.h>
 
-#ifdef __SMM__
-#include <arch/io.h>
-#else
-# include <device/device.h>
-# include <device/pci.h>
+#ifndef __SMM__
+#include <device/device.h>
+#include <device/pci.h>
 #endif
 
 #include "me.h"
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index a108840b32..03d26876df 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -28,7 +28,6 @@
 #include "nvs.h"
 
 #include <northbridge/intel/sandybridge/sandybridge.h>
-#include <arch/io.h>
 #include <southbridge/intel/bd82x6x/me.h>
 #include <southbridge/intel/common/gpio.h>
 #include <cpu/intel/model_206ax/model_206ax.h>
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 31cdb3391d..71655bc0fd 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -37,7 +37,6 @@
 
 
 #ifdef __SMM__
-#include <arch/io.h>
 #define pci_read_config_byte(dev, reg, targ)\
 	*(targ) = pci_read_config8(dev, reg)
 #define pci_read_config_word(dev, reg, targ)\
@@ -52,7 +51,6 @@
 	pci_write_config32(dev, reg, val)
 #else /* !__SMM__ */
 #include <device/device.h>
-#include <device/pci.h>
 #define pci_read_config_byte(dev, reg, targ)\
 	*(targ) = pci_read_config8(dev, reg)
 #define pci_read_config_word(dev, reg, targ)\
diff --git a/src/southbridge/intel/fsp_rangeley/early_init.c b/src/southbridge/intel/fsp_rangeley/early_init.c
index ba4ebe061c..1ef8cb2add 100644
--- a/src/southbridge/intel/fsp_rangeley/early_init.c
+++ b/src/southbridge/intel/fsp_rangeley/early_init.c
@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <pc80/mc146818rtc.h>
 #include <version.h>
-#include <device/pci_def.h>
 #include "pci_devs.h"
 #include "soc.h"
 
diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c
index 726fd3b9ef..3e7c17a74e 100644
--- a/src/southbridge/intel/fsp_rangeley/lpc.c
+++ b/src/southbridge/intel/fsp_rangeley/lpc.c
@@ -29,7 +29,6 @@
 #include <elog.h>
 #include <string.h>
 #include <cbmem.h>
-#include <arch/acpi.h>
 #include <arch/acpigen.h>
 #include "soc.h"
 #include "irq.h"
diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h
index 09172016e8..ffadee4bf2 100644
--- a/src/southbridge/intel/fsp_rangeley/soc.h
+++ b/src/southbridge/intel/fsp_rangeley/soc.h
@@ -62,7 +62,6 @@ int soc_silicon_type(void);
 int soc_silicon_supported(int type, int rev);
 void soc_enable(struct device *dev);
 
-#include <arch/acpi.h>
 void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt);
 
 #if IS_ENABLED(CONFIG_ELOG)
diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c
index 98ae708070..97548069ad 100644
--- a/src/southbridge/intel/fsp_rangeley/spi.c
+++ b/src/southbridge/intel/fsp_rangeley/spi.c
@@ -29,7 +29,6 @@
 static int ich_status_poll(u16 bitmask, int wait_til_set);
 
 #ifdef __SMM__
-#include <arch/io.h>
 #define pci_read_config_byte(dev, reg, targ)\
 	*(targ) = pci_read_config8(dev, reg)
 #define pci_read_config_word(dev, reg, targ)\
diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c
index 0d75350572..b1ff815edb 100644
--- a/src/southbridge/intel/ibexpeak/me.c
+++ b/src/southbridge/intel/ibexpeak/me.c
@@ -31,11 +31,9 @@
 #include <delay.h>
 #include <elog.h>
 
-#ifdef __SMM__
-#include <arch/io.h>
-#else
-# include <device/device.h>
-# include <device/pci.h>
+#ifndef __SMM__
+#include <device/device.h>
+#include <device/pci.h>
 #endif
 
 #include "me.h"
diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c
index 4da76cf558..b70273c76c 100644
--- a/src/southbridge/intel/ibexpeak/smihandler.c
+++ b/src/southbridge/intel/ibexpeak/smihandler.c
@@ -34,7 +34,6 @@
  */
 #include <northbridge/intel/nehalem/nehalem.h>
 #include <southbridge/intel/common/gpio.h>
-#include <arch/io.h>
 
 /* While we read PMBASE dynamically in case it changed, let's
  * initialize it with a sane value
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 3b8644a96d..8a5f3aca44 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -33,7 +33,6 @@
 #include "nvs.h"
 #include "pch.h"
 #include <arch/acpigen.h>
-#include <cbmem.h>
 #include <drivers/intel/gma/i915.h>
 #include <southbridge/intel/common/acpi_pirq_gen.h>
 #include <southbridge/intel/common/rtc.h>
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 5850ab564e..a02be811f6 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -174,7 +174,6 @@ void disable_gpe(u32 mask);
 
 #if !defined(__PRE_RAM__) && !defined(__SMM__)
 #include <device/device.h>
-#include <arch/acpi.h>
 #include "chip.h"
 void pch_enable(struct device *dev);
 void pch_disable_devfn(struct device *dev);
diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c
index b6bb1f8d3a..3ac6464910 100644
--- a/src/southbridge/nvidia/mcp55/lpc.c
+++ b/src/southbridge/nvidia/mcp55/lpc.c
@@ -33,7 +33,6 @@
 #include <arch/acpi.h>
 #include <stdlib.h>
 #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
-#include <arch/acpi.h>
 #include <arch/acpigen.h>
 #endif
 #include <cpu/amd/powernow.h>