diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-11-01 19:13:08 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2018-11-23 21:54:41 +0000 |
| commit | f385e9d253bdc83a5cda4d56cacafa1c98a52335 (patch) | |
| tree | 0646a6760d361d71fadbbaaaba31888b9d897288 /src/southbridge | |
| parent | 386b084ee187e7705d16c7f67f28b62d02eb9ca9 (diff) | |
| download | coreboot-f385e9d253bdc83a5cda4d56cacafa1c98a52335.tar.xz | |
sb/intel/bd82x6x/early_usb.c: Fix formatting
Remove whitespace between the function name and open
parenthesis, and fix 81+ characters lines.
Unnecessary comment about 'include sandybridge.h'removed.
Change-Id: I0db1263ec11240003fe1f7080c758994fc0224d3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29428
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_usb.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index d4ff7837b9..1044953d7c 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -17,11 +17,10 @@ #include <arch/io.h> #include <device/pci_ids.h> #include <device/pci_def.h> -#include <northbridge/intel/sandybridge/sandybridge.h> /* For DEFAULT_RCBABASE. */ +#include <northbridge/intel/sandybridge/sandybridge.h> #include "pch.h" -void -early_usb_init (const struct southbridge_usb_port *portmap) +void early_usb_init(const struct southbridge_usb_port *portmap) { u32 reg32; const u32 rcba_dump[8] = { @@ -35,41 +34,42 @@ early_usb_init (const struct southbridge_usb_port *portmap) /* Activate PMBAR. */ pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ + /* Enable ACPI BAR */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Unlock registers. */ outw(inw(DEFAULT_PMBASE | UPRWC) | UPRWC_WR_EN, DEFAULT_PMBASE | UPRWC); for (i = 0; i < 14; i++) - write32 (DEFAULT_RCBABASE + (0x3500 + 4 * i), + write32(DEFAULT_RCBABASE + (0x3500 + 4 * i), currents[portmap[i].current]); for (i = 0; i < 10; i++) - write32 (DEFAULT_RCBABASE + (0x3538 + 4 * i), 0); + write32(DEFAULT_RCBABASE + (0x3538 + 4 * i), 0); for (i = 0; i < 8; i++) - write32 (DEFAULT_RCBABASE + (0x3560 + 4 * i), rcba_dump[i]); + write32(DEFAULT_RCBABASE + (0x3560 + 4 * i), rcba_dump[i]); for (i = 0; i < 8; i++) - write32 (DEFAULT_RCBABASE + (0x3580 + 4 * i), 0); + write32(DEFAULT_RCBABASE + (0x3580 + 4 * i), 0); reg32 = 0; for (i = 0; i < 14; i++) if (!portmap[i].enabled) reg32 |= (1 << i); - write32 (DEFAULT_RCBABASE + USBPDO, reg32); + write32(DEFAULT_RCBABASE + USBPDO, reg32); reg32 = 0; for (i = 0; i < 8; i++) if (portmap[i].enabled && portmap[i].oc_pin >= 0) reg32 |= (1 << (i + 8 * portmap[i].oc_pin)); - write32 (DEFAULT_RCBABASE + USBOCM1, reg32); + write32(DEFAULT_RCBABASE + USBOCM1, reg32); reg32 = 0; for (i = 8; i < 14; i++) if (portmap[i].enabled && portmap[i].oc_pin >= 4) reg32 |= (1 << (i - 8 + 8 * (portmap[i].oc_pin - 4))); - write32 (DEFAULT_RCBABASE + USBOCM2, reg32); + write32(DEFAULT_RCBABASE + USBOCM2, reg32); for (i = 0; i < 22; i++) - write32 (DEFAULT_RCBABASE + (0x35a8 + 4 * i), 0); + write32(DEFAULT_RCBABASE + (0x35a8 + 4 * i), 0); - pci_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000); + pci_write_config32(PCI_DEV(0, 0x14, 0), 0xe4, 0x00000000); /* Relock registers. */ outw(0, DEFAULT_PMBASE | UPRWC); |