device/pci_ops: Drop unused parameter

Drop the bus parameter, we do not use it.

It would still be possible to do per-bus selection
by evaluating the bus number, but currently we do
not have need for that either.

Change-Id: I09e928b4677d9db2eee12730ba7b3fdd8837805c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

2 files changed, 24 insertions, 26 deletions

diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c
index c5e38c130c..28e337f5d0 100644
--- a/src/southbridge/amd/rs780/rs780.c
+++ b/src/southbridge/amd/rs780/rs780.c
@@ -31,33 +31,32 @@ void static rs780_config_misc_clk(struct device *nb_dev)
 	u32 reg;
 	u16 word;
 	u8 byte;
-	struct bus pbus; /* fake bus for dev0 fun1 */
 
 	reg = pci_read_config32(nb_dev, 0x4c);
 	reg |= 1 << 0;
 	pci_write_config32(nb_dev, 0x4c, reg);
 
-	word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xf8);
+	word = pci_cf8_conf1.read16(0, 1, 0xf8);
 	word &= 0xf00;
-	pci_cf8_conf1.write16(&pbus, 0, 1, 0xf8, word);
+	pci_cf8_conf1.write16(0, 1, 0xf8, word);
 
-	word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xe8);
+	word = pci_cf8_conf1.read16(0, 1, 0xe8);
 	word &= ~((1 << 12) | (1 << 13) | (1 << 14));
 	word |= 1 << 13;
-	pci_cf8_conf1.write16(&pbus, 0, 1, 0xe8, word);
+	pci_cf8_conf1.write16(0, 1, 0xe8, word);
 
-	reg =  pci_cf8_conf1.read32(&pbus, 0, 1, 0x94);
+	reg =  pci_cf8_conf1.read32(0, 1, 0x94);
 	reg &= ~((1 << 16) | (1 << 24) | (1 << 28));
-	pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
+	pci_cf8_conf1.write32(0, 1, 0x94, reg);
 
-	reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x8c);
+	reg = pci_cf8_conf1.read32(0, 1, 0x8c);
 	reg &= ~((1 << 13) | (1 << 14) | (1 << 24) | (1 << 25));
 	reg |= 1 << 13;
-	pci_cf8_conf1.write32(&pbus, 0, 1, 0x8c, reg);
+	pci_cf8_conf1.write32(0, 1, 0x8c, reg);
 
-	reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc);
+	reg = pci_cf8_conf1.read32(0, 1, 0xcc);
 	reg |= 1 << 24;
-	pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg);
+	pci_cf8_conf1.write32(0, 1, 0xcc, reg);
 
 	reg = nbmc_read_index(nb_dev, 0x7a);
 	reg &= ~0x3f;
@@ -66,31 +65,31 @@ void static rs780_config_misc_clk(struct device *nb_dev)
 	set_htiu_enable_bits(nb_dev, 0x05, 1 << 11, 1 << 11);
 	nbmc_write_index(nb_dev, 0x7a, reg);
 	/* Powering Down efuse and strap block clocks after boot-up. GFX Mode. */
-	reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc);
+	reg = pci_cf8_conf1.read32(0, 1, 0xcc);
 	reg &= ~(1 << 23);
 	reg |= 1 << 24;
-	pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg);
+	pci_cf8_conf1.write32(0, 1, 0xcc, reg);
 
 	/* Programming NB CLK table. */
-	byte = pci_cf8_conf1.read8(&pbus, 0, 1, 0xe0);
+	byte = pci_cf8_conf1.read8(0, 1, 0xe0);
 	byte |= 0x01;
-	pci_cf8_conf1.write8(&pbus, 0, 1, 0xe0, byte);
+	pci_cf8_conf1.write8(0, 1, 0xe0, byte);
 
 #if 0
 	/* Powerdown reference clock to graphics core PLL in northbridge only mode */
-	reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x8c);
+	reg = pci_cf8_conf1.read32(0, 1, 0x8c);
 	reg |= 1 << 21;
-	pci_cf8_conf1.write32(&pbus, 0, 1, 0x8c, reg);
+	pci_cf8_conf1.write32(0, 1, 0x8c, reg);
 
 	/* Powering Down efuse and strap block clocks after boot-up. NB Only Mode. */
-	reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc);
+	reg = pci_cf8_conf1.read32(0, 1, 0xcc);
 	reg |= (1 << 23) | (1 << 24);
-	pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg);
+	pci_cf8_conf1.write32(0, 1, 0xcc, reg);
 
 	/* Powerdown clock to memory controller in northbridge only mode */
-	byte = pci_cf8_conf1.read8(&pbus, 0, 1, 0xe4);
+	byte = pci_cf8_conf1.read8(0, 1, 0xe4);
 	byte |= 1 << 0;
-	pci_cf8_conf1.write8(&pbus, 0, 1, 0xe4, reg);
+	pci_cf8_conf1.write8(0, 1, 0xe4, reg);
 
 	/* CLKCFG:0xE8 Bit[17] = 0x1	 Powerdown clock to IOC GFX block in no external graphics mode */
 	/* TODO: */
diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c
index 9d4c689759..763dd014af 100644
--- a/src/southbridge/amd/sr5650/pcie.c
+++ b/src/southbridge/amd/sr5650/pcie.c
@@ -888,7 +888,6 @@ void config_gpp_core(struct device *nb_dev, struct device *sb_dev)
 void pcie_config_misc_clk(struct device *nb_dev)
 {
 	u32 reg;
-	//struct bus pbus; /* fake bus for dev0 fun1 */
 
 	reg = pci_read_config32(nb_dev, 0x4c);
 	reg |= 1 << 0;
@@ -902,9 +901,9 @@ void pcie_config_misc_clk(struct device *nb_dev)
 		set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_GFX, (3 << 6) | (~0xf), 3 << 6);
 
 		/* LCLK Clock Gating */
-		reg =  pci_cf8_conf1.read32(&pbus, 0, 1, 0x94);
+		reg =  pci_cf8_conf1.read32(0, 1, 0x94);
 		reg &= ~(1 << 16);
-		pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
+		pci_cf8_conf1.write32(0, 1, 0x94, reg);
 	}
 
 	if (AtiPcieCfg.Config & PCIE_GPP_CLK_GATING) {
@@ -914,9 +913,9 @@ void pcie_config_misc_clk(struct device *nb_dev)
 		set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_SB, (3 << 6) | (~0xf), 3 << 6);
 
 		/* LCLK Clock Gating */
-		reg =  pci_cf8_conf1.read32(&pbus, 0, 1, 0x94);
+		reg =  pci_cf8_conf1.read32(0, 1, 0x94);
 		reg &= ~(1 << 24);
-		pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
+		pci_cf8_conf1.write32(0, 1, 0x94, reg);
 	}
 #endif