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| author | Martin Roth <martin@se-eng.com> | 2013-01-14 15:46:38 -0700 |
|---|---|---|
| committer | Paul Menzel <paulepanter@users.sourceforge.net> | 2013-01-16 23:59:08 +0100 |
| commit | 09574d5c3c920d2959336a25064f9651df39e30e (patch) | |
| tree | aab8236d51d077ee239d49168929056713b888bd /src/southbridge | |
| parent | a12eaccc0bbfd6f2b47fd5eb38574852a64ec749 (diff) | |
| download | coreboot-09574d5c3c920d2959336a25064f9651df39e30e.tar.xz | |
Fix high dword of MTRR mask set with CONFIG_CPU_ADDR_BITS
Bits were being shifted off the end of the mask accidentally.
This results in all masks being 32 bits wide instead of 48.
Change-Id: I5f4d1b6a323df1aa4568ff4491f82447b8a2f839
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2146
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/southbridge')
0 files changed, 0 insertions, 0 deletions