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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-03-18 10:55:06 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-03-19 04:00:08 +0100 |
| commit | 1e60839be09ee25acea3cf94f5954907c71bb0ad (patch) | |
| tree | d371e45bf8e46076193a1a04c7ce42ef5f23bd61 /src/southbridge | |
| parent | 8135dba368333e9112c9610f75427df23bbea8a4 (diff) | |
| download | coreboot-1e60839be09ee25acea3cf94f5954907c71bb0ad.tar.xz | |
southbridge/amd/rs780: Remove requirement for CF8/CFC config access
The AMD RS780 early initialization code originally used the
CF8/CFC I/O method for PCI configuration space access. After
the default configuration access method was changed to MMIO
(http://review.coreboot.org/#q,aad07472), booting would hang
at "PCI: pci_scan_bus for bus 01". Fix the problem by changing
function rs780_nb_gfx_dev_table() so that it no longer borrows
the BAR3 address needed for PCIe MMIO config usage.
Change-Id: I8816b94c848e1b50f8c880e5867a96ca2a33a8a7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8394
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/amd/rs780/rs780.c | 26 |
1 files changed, 4 insertions, 22 deletions
diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c index dc5b9e45e9..c30febf052 100644 --- a/src/southbridge/amd/rs780/rs780.c +++ b/src/southbridge/amd/rs780/rs780.c @@ -190,28 +190,17 @@ static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev) { /* NB_InitGFXStraps */ u32 MMIOBase, apc04, apc18, apc24, romstrap2; - msr_t pcie_mmio_save = { 0, 0 }; volatile u32 * strap; - // disable processor pcie mmio, if enabled - if (is_family10h()) { - msr_t temp; - pcie_mmio_save = temp = rdmsr (0xc0010058); - temp.lo &= ~1; - wrmsr (0xc0010058, temp); - } - - /* Get PCIe configuration space. */ - MMIOBase = pci_read_config32(nb_dev, 0x1c) & 0xfffffff0; - /* Temporarily disable PCIe configuration space. */ - set_htiu_enable_bits(nb_dev, 0x32, 1<<28, 0); + /* Choose a base address that is unused and routed to the RS780. */ + MMIOBase = 0xFFB00000; - // 1E: NB_BIF_SPARE + /* 1E: NB_BIF_SPARE */ set_nbmisc_enable_bits(nb_dev, 0x1e, 0xffffffff, 1<<1 | 1<<4 | 1<<6 | 1<<7); /* Set a temporary Bus number. */ apc18 = pci_read_config32(dev, 0x18); pci_write_config32(dev, 0x18, 0x010100); - /* Set MMIO for AGP target(graphics controller). base = 0xe0000000, limit = 0x20000 */ + /* Set MMIO window for AGP target(graphics controller). */ apc24 = pci_read_config32(dev, 0x24); pci_write_config32(dev, 0x24, (MMIOBase>>16)+((MMIOBase+0x20000)&0xffff0000)); /* Enable memory access. */ @@ -262,13 +251,6 @@ static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev) pci_write_config32(dev, 0x18, apc18); pci_write_config32(dev, 0x24, apc24); - /* Enable PCIe configuration space. */ - set_htiu_enable_bits(nb_dev, 0x32, 0, 1<<28); - - // restore processor pcie mmio - if (is_family10h()) - wrmsr (0xc0010058, pcie_mmio_save); - printk(BIOS_INFO, "GC is accessible from now on.\n"); } |