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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-04-27 05:25:06 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-01 06:25:57 +0000 |
| commit | 804a34022cbd020e1b1f461ee3a45a68f14684f0 (patch) | |
| tree | 922e7e7a4d33007fe1b6963b3b415364487f549b /src/southbridge | |
| parent | d82faa8ea3f81087af76f9599e04258006dec222 (diff) | |
| download | coreboot-804a34022cbd020e1b1f461ee3a45a68f14684f0.tar.xz | |
sb/common/smihandler: Fix 16-bit read/write to PCI_COMMAND register
Change-Id: Ib403f5a231f86bdc60b956e72a4ae631aa6a3899
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/common/smihandler.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 7d4066da29..7b27ce0cd5 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -61,7 +61,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { - u32 reg32; + u16 reg16; pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); @@ -71,9 +71,9 @@ static void busmaster_disable_on_bus(int bus) continue; /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, reg16); /* If this is a bridge, then follow it. */ hdr = pci_read_config8(dev, PCI_HEADER_TYPE); |