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| author | Eric Biederman <ebiederm@xmission.com> | 2003-07-21 23:30:29 +0000 |
|---|---|---|
| committer | Eric Biederman <ebiederm@xmission.com> | 2003-07-21 23:30:29 +0000 |
| commit | 860ad373efdadde9bbc11ee49b8967a6428a404c (patch) | |
| tree | ba8afe4d78c341f27bd2511209c14024a98b4d54 /src/southbridge | |
| parent | 2c018fba95a5f40c4eaaa20421e8c893dffdb62e (diff) | |
| download | coreboot-860ad373efdadde9bbc11ee49b8967a6428a404c.tar.xz | |
- First pass at code for generic link width and size determination
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@999 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/amd/amd8131/amd8131_bridge.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/southbridge/amd/amd8131/amd8131_bridge.c b/src/southbridge/amd/amd8131/amd8131_bridge.c index 9ef83da50d..ded5480234 100644 --- a/src/southbridge/amd/amd8131/amd8131_bridge.c +++ b/src/southbridge/amd/amd8131/amd8131_bridge.c @@ -9,6 +9,28 @@ static void pcix_init(device_t dev) { + uint16_t word; + uint8_t byte; + + + /* Enable memory write and invalidate ??? */ + byte = pci_read_config8(dev, 0x04); + byte |= 0x10; + pci_write_config8(dev, 0x04, byte); + + /* Set drive strength */ + word = pci_read_config16(dev, 0xe0); + word = 0x0404; + pci_write_config16(dev, 0xe0, word); + word = pci_read_config16(dev, 0xe4); + word = 0x0404; + pci_write_config16(dev, 0xe4, word); + + /* Set impedance */ + word = pci_read_config16(dev, 0xe8); + word = 0x0404; + pci_write_config16(dev, 0xe8, word); + return; } |