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authorDuncan Laurie <dlaurie@chromium.org>2012-06-23 15:43:41 -0700
committerPatrick Georgi <patrick@georgi-clan.de>2012-07-24 15:00:54 +0200
commit8e515d36b467a1457bab8947ccf4ddf61a85ac8f (patch)
tree836107c2ce38717368ebf85ef3886d89383d4567 /src/southbridge
parent9a380abaa2c96c9e937327a43e13d700c722df6d (diff)
downloadcoreboot-8e515d36b467a1457bab8947ccf4ddf61a85ac8f.tar.xz
RTC: Enable extended CMOS in the bootblock
This makes it available early in romstage without having to worry when the different romstagse enable it. Check for extended CMOS to be enabled in early romstage. This is used by a later commit which uses the extended CMOS region for stoage. Change-Id: I9e026d48499c63d6503c2b020d4cc3047126fa93 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1306 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/bd82x6x/bootblock.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c
index d6cba5f3c5..0191bbfc7f 100644
--- a/src/southbridge/intel/bd82x6x/bootblock.c
+++ b/src/southbridge/intel/bd82x6x/bootblock.c
@@ -72,4 +72,7 @@ static void bootblock_southbridge_init(void)
#endif
enable_spi_prefetch();
enable_port80_on_lpc();
+
+ /* Enable upper 128bytes of CMOS */
+ RCBA32(RC) = (1 << 2);
}