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| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2011-10-30 20:30:48 +0100 |
|---|---|---|
| committer | Rudolf Marek <r.marek@assembler.cz> | 2011-10-30 20:49:15 +0100 |
| commit | af3dce981db63eb16d127347264a46247ed893bb (patch) | |
| tree | ef118ee91074d07883c59e709298284770076621 /src/southbridge | |
| parent | 54a5aedec69bac62bf9bb5f65e431130507235fb (diff) | |
| download | coreboot-af3dce981db63eb16d127347264a46247ed893bb.tar.xz | |
Fix gcc 4.6.1 breakage of southbridge/amd/sr5650/pcie.c.
Change-Id: I3ccb3860207e1b3ccac4313f7b537c434af5166f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/360
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Diffstat (limited to 'src/southbridge')
| -rwxr-xr-x | src/southbridge/amd/sr5650/pcie.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c index 37743cacae..eebe711cdb 100755 --- a/src/southbridge/amd/sr5650/pcie.c +++ b/src/southbridge/amd/sr5650/pcie.c @@ -370,8 +370,8 @@ static void gpp3a_cpl_buf_alloc(device_t nb_dev, device_t dev) slave_cpl = (u8 *)&pGpp111111; break; default: /* shouldn't be here. */ - printk(BIOS_DEBUG, "buggy gpp3a_configuration\n"); - break; + printk(BIOS_WARNING, "buggy gpp3a_configuration\n"); + return; } value = slave_cpl[dev_index - 4]; |