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authorMarshall Dawson <marshalldawson3rd@gmail.com>2017-10-19 09:45:16 -0600
committerAaron Durbin <adurbin@chromium.org>2018-02-16 22:38:50 +0000
commitc0dbedac431a2038cd7382d4c0cd8ccb958675ac (patch)
tree646e35c9c9076a54be405082a29205fd72198f5c /src/southbridge
parented089376e39b85af61b8db6904627d294f31c55b (diff)
downloadcoreboot-c0dbedac431a2038cd7382d4c0cd8ccb958675ac.tar.xz
x86/mtrr: Enable Rd/WrDram mod in AMD fixed MTRRs
AMD's fixed MTRRs have RdDram and WrDram bits that route memory accesses to DRAM vs. MMIO. These are typically hidden for normal operation by clearing SYS_CFG[19] (MtrrFixDramModEn). According to BKDGs and AMD64 Programmer's Manual vol 2, this bit is clear at reset, should be set for configuration during POST, then cleared for normal operation. Attempting to modify the RdDram and WrDram settings without unhiding them causes a General Protection Fault. Add functions to enable and disable MtrrFixDramModEn. Unhide/hide as necessary when copying or writing the fixed MTRRs. Finally, modify sipi_vector.S to enable the bits prior to writing the fixed MTRRs and disable when complete. This functionality is compiled out on non-AMD platforms. BUG=b:68019051 TEST=Boot Kahlee, check steps with HDT Change-Id: Ie195131ff752400eb886dfccc39b314b4fa6b3f3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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