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| author | Shelley Chen <shchen@google.com> | 2019-03-12 19:01:18 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-14 11:28:31 +0000 |
| commit | c3de6203a75fb31ca7f4f222aad0560e39feffe0 (patch) | |
| tree | 385895f691be7c127e92241310f9d08a474f1314 /src/southbridge | |
| parent | 38e27c3e92ac2588173bb547944c9b5aaa00536a (diff) | |
| download | coreboot-c3de6203a75fb31ca7f4f222aad0560e39feffe0.tar.xz | |
mb/google/hatch: fix RCompResistor[0] value
From doc#573387 CML System Memory DQ DQS Rcomp Mapping Information
User Guide, RCompResistor[0] should be 121.
BUG=b:122959294
BRANCH=None
TEST=emerge coreboot and make sure boots up
Change-Id: If69e7fb41e79d88d21b0e50fb65107a1686d696a
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31868
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge')
0 files changed, 0 insertions, 0 deletions