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authorStefan Reinauer <stepan@coresystems.de>2010-03-17 04:37:52 +0000
committerStefan Reinauer <stepan@openbios.org>2010-03-17 04:37:52 +0000
commitcfef7dff9b80b42e2c9373e8c80d8e5ba2bf8d02 (patch)
tree5861a6388449f7a63ee0a04c50e0c3ff2ea804af /src/southbridge
parent3c486f8f76b2ad526538af14cf5cf74fcf627ba9 (diff)
downloadcoreboot-cfef7dff9b80b42e2c9373e8c80d8e5ba2bf8d02.tar.xz
Actually enable HPET
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/i82801dx/i82801dx_lpc.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/southbridge/intel/i82801dx/i82801dx_lpc.c b/src/southbridge/intel/i82801dx/i82801dx_lpc.c
index 0aff9f4560..181f5454e1 100644
--- a/src/southbridge/intel/i82801dx/i82801dx_lpc.c
+++ b/src/southbridge/intel/i82801dx/i82801dx_lpc.c
@@ -193,7 +193,8 @@ static void enable_hpet(struct device *dev)
*/
reg32 &= ~(3 << 15); /* Clear it */
reg32 |= (code << 15);
- /* TODO: reg32 is never written to anywhere? */
+ pci_write_config32(dev, GEN_CNTL, reg32);
+
printk_debug("Enabling HPET @0x%x\n", HPET_ADDR | (code << 12));
}