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| author | Stefan Reinauer <stepan@coresystems.de> | 2010-04-15 23:01:59 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-04-15 23:01:59 +0000 |
| commit | e46c1c85c90b6d263f951ab745a9fadd93041111 (patch) | |
| tree | 4ffefdc0767139b66c48732d44b8a3222eb6b09f /src/southbridge | |
| parent | c24d383c15f6d31cd1dd5fb8e090db0561421599 (diff) | |
| download | coreboot-e46c1c85c90b6d263f951ab745a9fadd93041111.tar.xz | |
remove more warnings. move ROOT_COMPLEX selection to fam10
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5447 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/amd/rs690/rs690_gfx.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/rs780/rs780_gfx.c | 10 |
2 files changed, 10 insertions, 2 deletions
diff --git a/src/southbridge/amd/rs690/rs690_gfx.c b/src/southbridge/amd/rs690/rs690_gfx.c index 887c38e8de..c55f2bc3d3 100644 --- a/src/southbridge/amd/rs690/rs690_gfx.c +++ b/src/southbridge/amd/rs690/rs690_gfx.c @@ -34,7 +34,7 @@ #define CLK_CNTL_INDEX 0x8 #define CLK_CNTL_DATA 0xC -#if 0 +#ifdef UNUSED_CODE static u32 clkind_read(device_t dev, u32 index) { u32 gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF; diff --git a/src/southbridge/amd/rs780/rs780_gfx.c b/src/southbridge/amd/rs780/rs780_gfx.c index 7c951ef42d..90dc0cd29a 100644 --- a/src/southbridge/amd/rs780/rs780_gfx.c +++ b/src/southbridge/amd/rs780/rs780_gfx.c @@ -39,12 +39,17 @@ void set_pcie_reset(void); void set_pcie_dereset(void); +/* Trust the original resource allocation. Don't do it again. */ +#undef DONT_TRUST_RESOURCE_ALLOCATION +//#define DONT_TRUST_RESOURCE_ALLOCATION + #define CLK_CNTL_INDEX 0x8 #define CLK_CNTL_DATA 0xC /* The Integrated Info Table. */ ATOM_INTEGRATED_SYSTEM_INFO_V2 vgainfo; +#ifdef UNUSED_CODE static u32 clkind_read(device_t dev, u32 index) { u32 gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF; @@ -52,6 +57,7 @@ static u32 clkind_read(device_t dev, u32 index) *(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index & 0x7F; return *(u32*)(gfx_bar2+CLK_CNTL_DATA); } +#endif static void clkind_write(device_t dev, u32 index, u32 data) { @@ -174,6 +180,7 @@ static u8 FinalizeMMIO(MMIORANGE *pMMIO) return n; } +#ifdef DONT_TRUST_RESOURCE_ALLOCATION static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO) { CIM_STATUS Status = CIM_UNSUPPORTED; @@ -288,6 +295,7 @@ static void ProgramMMIO(MMIORANGE *pMMIO, u8 LinkID, u8 Attribute) pci_write_config32(k8_f1, 0x80+MmioReg*8, Base); } } +#endif static void internal_gfx_pci_dev_init(struct device *dev) { @@ -490,7 +498,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) pci_write_config8(dev, 0x4, temp8); } -#if 0 /* Trust the original resource allocation. Don't do it again. */ +#ifdef DONT_TRUST_RESOURCE_ALLOCATION /* NB_SetupMGMMIO. */ /* clear MMIO and CreativeMMIO. */ |