lynxpoint: Add ACPI Method to enable GPIO as wake source

This is an LPT-LP specific method that will enable a specific
GPIO as an ACPI SCI wake source.

It can be used by a device _DSW method to enable a pin that is
otherwise not configured to generate SCI at runtime.

It will set:
- GPIO owner to ACPI
- GPIO route to SCI
- GPIO config to GPIO, Input, Inverted

Also clean up and remove ACPI field definitions that are unused
and/or incorrect.

Change-Id: I14acc2de50e6200f61c2898a7bd1252400e0f0be
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56621
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4189
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

3 files changed, 97 insertions, 185 deletions

diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl
index 7e2692637a..07b3fcf745 100644
--- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl
@@ -32,6 +32,8 @@ Device (LPCB)
 		DIDH,	8,	// Device ID High Byte
 		Offset (0x40),
 		PMBS,	16,	// PMBASE
+		Offset (0x48),
+		GPBS,   16,	// GPIOBASE
 		Offset (0x60),	// Interrupt Routing Registers
 		PRTA,	8,
 		PRTB,	8,
@@ -47,24 +49,6 @@ Device (LPCB)
 		IOD0,	8,
 		IOD1,	8,
 
-		Offset (0xb8),	// GPIO Routing Control
-		GR00,	 2,
-		GR01,	 2,
-		GR02,	 2,
-		GR03,	 2,
-		GR04,	 2,
-		GR05,	 2,
-		GR06,	 2,
-		GR07,	 2,
-		GR08,	 2,
-		GR09,	 2,
-		GR10,	 2,
-		GR11,	 2,
-		GR12,	 2,
-		GR13,	 2,
-		GR14,	 2,
-		GR15,	 2,
-
 		Offset (0xf0),	// RCBA
 		RCEN,	1,
 		,	13,
diff --git a/src/southbridge/intel/lynxpoint/acpi/lpt_lp.asl b/src/southbridge/intel/lynxpoint/acpi/lpt_lp.asl
new file mode 100644
index 0000000000..fd64cb8cbc
--- /dev/null
+++ b/src/southbridge/intel/lynxpoint/acpi/lpt_lp.asl
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* LynxPoint-H */
+
+Scope (\_SB.PCI0.LPCB)
+{
+	// GWAK: Setup GPIO as ACPI GPE for Wake
+	// Arg0: GPIO Number
+	Method (GWAK, 1, NotSerialized)
+	{
+		// Local0 = GPIO Base Address
+		Store (And (GPBS, Not(0x1)), Local0)
+
+		// Local1 = BANK, Local2 = OFFSET
+		Divide (Arg0, 32, Local2, Local1)
+
+		//
+		// Set OWNER to ACPI
+		//
+
+		// Local3 = GPIOBASE + GPIO_OWN(BANK)
+		Store (Add (Local0, Multiply (Local1, 0x4)), Local3)
+
+		// GPIO_OWN(BANK)
+		OperationRegion (IOWN, SystemIO, Local3, 4)
+		Field (IOWN, AnyAcc, NoLock, Preserve) {
+			GOWN, 32,
+		}
+
+		// GPIO_OWN[GPIO] = 0 (ACPI)
+		Store (And (GOWN, Not (ShiftLeft (0x1, Local2))), GOWN)
+
+		//
+		// Set ROUTE to SCI
+		//
+
+		// Local3 = GPIOBASE + GPIO_ROUTE(BANK)
+		Store (Add (Add (Local0, 0x30), Multiply (Local1, 0x4)), Local3)
+
+		// GPIO_ROUTE(BANK)
+		OperationRegion (IROU, SystemIO, Local3, 4)
+		Field (IROU, AnyAcc, NoLock, Preserve) {
+			GROU, 32,
+		}
+
+		// GPIO_ROUTE[GPIO] = 0 (SCI)
+		Store (And (GROU, Not (ShiftLeft (0x1, Local2))), GROU)
+
+		//
+		// Set GPnCONFIG to GPIO|INPUT|INVERT
+		//
+
+		// Local3 = GPIOBASE + GPnCONFIG0(GPIO)
+		Store (Add (Add (Local0, 0x100), Multiply (Arg0, 0x8)), Local3)
+
+		// GPnCONFIG(GPIO)
+		OperationRegion (GPNC, SystemIO, Local3, 8)
+		Field (GPNC, AnyAcc, NoLock, Preserve) {
+			GMOD, 1,  // MODE:   0=NATIVE 1=GPIO
+			, 1,
+			GIOS, 1,  // IO_SEL: 0=OUTPUT 1=INPUT
+			GINV, 1,  // INVERT: 0=NORMAL 1=INVERT
+			GLES, 1,  // LxEB:   0=EDGE 1=LEVEL
+			, 24,
+			ILVL, 1,  // INPUT:  0=LOW 1=HIGH
+			OLVL, 1,  // OUTPUT: 0=LOW 1=HIGH
+			GPWP, 2,  // PULLUP: 00=NONE 01=DOWN 10=UP 11=INVALID
+			ISEN, 1,  // SENSE:  0=ENABLE 1=DISABLE
+		}
+
+		Store (0x1, GMOD) // GPIO
+		Store (0x1, GIOS) // INPUT
+		Store (0x1, GINV) // INVERT
+	}
+}
\ No newline at end of file
diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl
index f5cf6aecf2..8ac55eb851 100644
--- a/src/southbridge/intel/lynxpoint/acpi/pch.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl
@@ -42,173 +42,6 @@ Scope(\)
 		TRP0, 8		// IO-Trap at 0x808
 	}
 
-	// PCH Power Management Registers, located at PMBASE (0x1f.0 0x40.l)
-	OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0xff)
-	Field(PMIO, ByteAcc, NoLock, Preserve)
-	{
-		Offset(0x20),	// GPE0_STS
-		, 16,
-		GS00, 1,	// GPIO00 SCI/Wake Status
-		GS01, 1,	// GPIO01 SCI/Wake Status
-		GS02, 1,	// GPIO02 SCI/Wake Status
-		GS03, 1,	// GPIO03 SCI/Wake Status
-		GS04, 1,	// GPIO04 SCI/Wake Status
-		GS05, 1,	// GPIO05 SCI/Wake Status
-		GS06, 1,	// GPIO06 SCI/Wake Status
-		GS07, 1,	// GPIO07 SCI/Wake Status
-		GS08, 1,	// GPIO08 SCI/Wake Status
-		GS09, 1,	// GPIO09 SCI/Wake Status
-		GS10, 1,	// GPIO10 SCI/Wake Status
-		GS11, 1,	// GPIO11 SCI/Wake Status
-		GS12, 1,	// GPIO12 SCI/Wake Status
-		GS13, 1,	// GPIO13 SCI/Wake Status
-		GS14, 1,	// GPIO14 SCI/Wake Status
-		GS15, 1,	// GPIO15 SCI/Wake Status
-		Offset(0x28),	// GPE0_EN
-		, 16,
-		GE00, 1,	// GPIO00 SCI/Wake Enable
-		GE01, 1,	// GPIO01 SCI/Wake Enable
-		GE02, 1,	// GPIO02 SCI/Wake Enable
-		GE03, 1,	// GPIO03 SCI/Wake Enable
-		GE04, 1,	// GPIO04 SCI/Wake Enable
-		GE05, 1,	// GPIO05 SCI/Wake Enable
-		GE06, 1,	// GPIO06 SCI/Wake Enable
-		GE07, 1,	// GPIO07 SCI/Wake Enable
-		GE08, 1,	// GPIO08 SCI/Wake Enable
-		GE09, 1,	// GPIO09 SCI/Wake Enable
-		GE10, 1,	// GPIO10 SCI/Wake Enable
-		GE11, 1,	// GPIO11 SCI/Wake Enable
-		GE12, 1,	// GPIO12 SCI/Wake Enable
-		GE13, 1,	// GPIO13 SCI/Wake Enable
-		GE14, 1,	// GPIO14 SCI/Wake Enable
-		GE15, 1,	// GPIO15 SCI/Wake Enable
-		Offset(0x42),	// General Purpose Control
-		, 1,		// skip 1 bit
-		GPEC, 1,	// SWGPE_CTRL
-	}
-
-	// GPIO IO mapped registers (0x1f.0 reg 0x48.l)
-	OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x6c)
-	Field(GPIO, ByteAcc, NoLock, Preserve)
-	{
-		Offset(0x00),	// GPIO Use Select
-		GU00, 8,
-		GU01, 8,
-		GU02, 8,
-		GU03, 8,
-		Offset(0x04),	// GPIO IO Select
-		GIO0, 8,
-		GIO1, 8,
-		GIO2, 8,
-		GIO3, 8,
-		Offset(0x0c),	// GPIO Level
-		GL00, 1,
-		GP01, 1,
-		GP02, 1,
-		GP0e, 1,
-		GP04, 1,
-		GP05, 1,
-		GP06, 1,
-		GP07, 1,
-		GP08, 1,
-		GP09, 1,
-		GP10, 1,
-		GP11, 1,
-		GP12, 1,
-		GP13, 1,
-		GP14, 1,
-		GP15, 1,
-		GP16, 1,
-		GP17, 1,
-		GP18, 1,
-		GP19, 1,
-		GP20, 1,
-		GP21, 1,
-		GP22, 1,
-		GP23, 1,
-		GP24, 1,
-		GP25, 1,
-		GP26, 1,
-		GP27, 1,
-		GP28, 1,
-		GP29, 1,
-		GP30, 1,
-		GP31, 1,
-		Offset(0x18),	// GPIO Blink
-		GB00, 8,
-		GB01, 8,
-		GB02, 8,
-		GB03, 8,
-		Offset(0x2c),	// GPIO Invert
-		GIV0, 8,
-		GIV1, 8,
-		GIV2, 8,
-		GIV3, 8,
-		Offset(0x30),	// GPIO Use Select 2
-		GU04, 8,
-		GU05, 8,
-		GU06, 8,
-		GU07, 8,
-		Offset(0x34),	// GPIO IO Select 2
-		GIO4, 8,
-		GIO5, 8,
-		GIO6, 8,
-		GIO7, 8,
-		Offset(0x38),	// GPIO Level 2
-		GP32, 1,
-		GP33, 1,
-		GP34, 1,
-		GP35, 1,
-		GP36, 1,
-		GP37, 1,
-		GP38, 1,
-		GP39, 1,
-		GP40, 1,
-		GP41, 1,
-		GP42, 1,
-		GP43, 1,
-		GP44, 1,
-		GP45, 1,
-		GP46, 1,
-		GP47, 1,
-		GP48, 1,
-		GP49, 1,
-		GP50, 1,
-		GP51, 1,
-		GP52, 1,
-		GP53, 1,
-		GP54, 1,
-		GP55, 1,
-		GP56, 1,
-		GP57, 1,
-		GP58, 1,
-		GP59, 1,
-		GP60, 1,
-		GP61, 1,
-		GP62, 1,
-		GP63, 1,
-		Offset(0x40),	// GPIO Use Select 3
-		GU08, 8,
-		GU09, 4,
-		Offset(0x44),	// GPIO IO Select 3
-		GIO8, 8,
-		GIO9, 4,
-		Offset(0x48),	// GPIO Level 3
-		GP64, 1,
-		GP65, 1,
-		GP66, 1,
-		GP67, 1,
-		GP68, 1,
-		GP69, 1,
-		GP70, 1,
-		GP71, 1,
-		GP72, 1,
-		GP73, 1,
-		GP74, 1,
-		GP75, 1,
-	}
-
-
 	// ICH7 Root Complex Register Block. Memory Mapped through RCBA)
 	OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000)
 	Field(RCRB, DWordAcc, Lock, Preserve)
@@ -270,6 +103,7 @@ Scope(\)
 // Serial IO
 #if CONFIG_INTEL_LYNXPOINT_LP
 #include "serialio.asl"
+#include "lpt_lp.asl"
 #endif
 
 Method (_OSC, 4)