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authorStefan Reinauer <stepan@coresystems.de>2010-03-17 04:40:15 +0000
committerStefan Reinauer <stepan@openbios.org>2010-03-17 04:40:15 +0000
commit50776fab1c9062ddfa353ee6c138f69d901c11b7 (patch)
treeece1cfdf3cf999616f895dd4aa4ad4f0713c38c7 /src/southbridge
parentdfd29aa41347083fbc7a26ca7d639f7f60fe1eea (diff)
downloadcoreboot-50776fab1c9062ddfa353ee6c138f69d901c11b7.tar.xz
trivial warning fixes, mostly for ACPI code
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5251 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/amd8111/amd8111_acpi.c5
-rw-r--r--src/southbridge/amd/amd8111/amd8111_nic.c6
2 files changed, 5 insertions, 6 deletions
diff --git a/src/southbridge/amd/amd8111/amd8111_acpi.c b/src/southbridge/amd/amd8111/amd8111_acpi.c
index f318b37621..67a789c08a 100644
--- a/src/southbridge/amd/amd8111/amd8111_acpi.c
+++ b/src/southbridge/amd/amd8111/amd8111_acpi.c
@@ -73,12 +73,12 @@ unsigned pm_base;
static void acpi_init(struct device *dev)
{
uint8_t byte;
- uint16_t word;
uint16_t pm10_bar;
uint32_t dword;
int on;
#if 0
+ uint16_t word;
printk_debug("ACPI: disabling NMI watchdog.. ");
byte = pci_read_config8(dev, 0x49);
pci_write_config8(dev, 0x49, byte | (1<<2));
@@ -98,9 +98,8 @@ static void acpi_init(struct device *dev)
word = pci_read_config16(dev, 0x46);
pci_write_config16(dev, 0x46, word | (1<<9));
printk_debug("done.\n");
-
-
#endif
+
/* To enable the register 0xcf9 in the IO space
* bit [D5] is set in the amd8111 configuration register.
* The config. reg. is devBx41. Register 0xcf9 allows
diff --git a/src/southbridge/amd/amd8111/amd8111_nic.c b/src/southbridge/amd/amd8111/amd8111_nic.c
index 98ac62b5d7..aa06253a46 100644
--- a/src/southbridge/amd/amd8111/amd8111_nic.c
+++ b/src/southbridge/amd/amd8111/amd8111_nic.c
@@ -54,12 +54,12 @@ static void nic_init(struct device *dev)
/* Hard Reset PHY */
printk_debug("Reseting PHY... ");
if (conf->phy_lowreset) {
- write32((void *)(mmio + CMD3), VAL0 | PHY_RST_POL | RESET_PHY);
+ write32((mmio + CMD3), VAL0 | PHY_RST_POL | RESET_PHY);
} else {
- write32((void *)(mmio + CMD3), VAL0 | RESET_PHY);
+ write32((mmio + CMD3), VAL0 | RESET_PHY);
}
mdelay(15);
- write32((void *)(mmio + CMD3), RESET_PHY);
+ write32((mmio + CMD3), RESET_PHY);
printk_debug("Done\n");
}