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authorFlorian Zumbiehl <florz@florz.de>2011-11-01 20:17:41 +0100
committerStefan Reinauer <stefan.reinauer@coreboot.org>2011-11-10 23:55:11 +0100
commit50dadfb1f8f8f9e1a0ea692652ae6b60b29a9f7e (patch)
tree3971f2cd1267386cc2f57c4def831b7b19151bcb /src/southbridge
parentbe7d8dcf8d2641ca413514e571f77f8aa7984d19 (diff)
downloadcoreboot-50dadfb1f8f8f9e1a0ea692652ae6b60b29a9f7e.tar.xz
compile code for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD
make code dependent on CONFIG_SOUTHBRIDGE_VIA_K8T800 also be included for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD Change-Id: I9f4624d08de2790fb513a88ed6207e28e7fbc733 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/374 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/via/k8t890/romstrap.inc2
-rw-r--r--src/southbridge/via/vt8237r/lpc.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/via/k8t890/romstrap.inc b/src/southbridge/via/k8t890/romstrap.inc
index 5b24948df5..a3814b096b 100644
--- a/src/southbridge/via/k8t890/romstrap.inc
+++ b/src/southbridge/via/k8t890/romstrap.inc
@@ -33,7 +33,7 @@ __romstrap_start:
* Below are some Dev0 Func2 HT control registers values,
* depending on strap pin, one of below lines is used.
*/
-#if CONFIG_SOUTHBRIDGE_VIA_K8M800 || CONFIG_SOUTHBRIDGE_VIA_K8T800
+#if CONFIG_SOUTHBRIDGE_VIA_K8M800 || CONFIG_SOUTHBRIDGE_VIA_K8T800 || CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD
tblpointer:
.long 0x50220000, 0X619707C2
diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index e59951702f..b1e1afe9c2 100644
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -298,7 +298,7 @@ static void vt8237r_init(struct device *dev)
pci_write_config8(dev, 0x48, 0x0c);
#else
- #if CONFIG_SOUTHBRIDGE_VIA_K8T800
+ #if CONFIG_SOUTHBRIDGE_VIA_K8T800 || CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD
/* It seems that when we pair with the K8T800, we need to disable
* the A2 mask
*/