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authorKyösti Mälkki <kyosti.malkki@gmail.com>2018-12-29 09:40:40 +0200
committerFelix Held <felix-coreboot@felixheld.de>2019-01-06 13:19:05 +0000
commit63649d24fd616dad397a4ae18f9aede43c6ce2dc (patch)
treedf6c66c50a330d79d81c315f43547f0fdc45978e /src/southbridge
parenta144e4d6fa93b9ba129b3aa8991cc5fb2ec3c8a6 (diff)
downloadcoreboot-63649d24fd616dad397a4ae18f9aede43c6ce2dc.tar.xz
usbdebug: Refactor init calls
Expose the function that can unconditionally re-initialise EHCI debug host and gadget. Given the missing header in soc/intel files that prevented building with USBDEBUG_IN_ROMSTAGE=y, it is not actually known if those SOCs work at all for usbdebug. Change-Id: I8ae7e144a89a8f7e5f9d307ba4e73d4f96401a79 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/fsp_rangeley/romstage.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c
index f986d79d36..bf92049479 100644
--- a/src/southbridge/intel/fsp_rangeley/romstage.c
+++ b/src/southbridge/intel/fsp_rangeley/romstage.c
@@ -24,6 +24,7 @@
#include <cpu/x86/lapic.h>
#include <cbmem.h>
#include <console/console.h>
+#include <console/usb.h>
#include <drivers/intel/fsp1_0/fsp_util.h>
#include <program_loading.h>
#include <northbridge/intel/fsp_rangeley/northbridge.h>
@@ -99,10 +100,9 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n",
__func__, (u32) status, (u32) hob_list_ptr);
-#if IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE)
/* FSP reconfigures USB, so reinit it to have debug */
- usbdebug_init();
-#endif /* IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) */
+ if (IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE))
+ usbdebug_hw_init(true);
printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status);