diff options
author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-10-12 17:34:08 +0000 |
---|---|---|
committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-10-12 17:34:08 +0000 |
commit | 74d1a6e8a166cd477f667a6fcb1e96b8a0cbdac1 (patch) | |
tree | 9cbdbe86bd282da60bfcbef7108ca6790bcde94e /src/southbridge | |
parent | 4ffde94c4ec51cdb24103ec13653e6f40513e1bb (diff) | |
download | coreboot-74d1a6e8a166cd477f667a6fcb1e96b8a0cbdac1.tar.xz |
We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it.
As both ioapic.h and acpi.h define a macro named "NMI", rename one
of them (NMI -> NMIType in acpi.h).
Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5943 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
28 files changed, 48 insertions, 42 deletions
diff --git a/src/southbridge/amd/amd8111/amd8111_lpc.c b/src/southbridge/amd/amd8111/amd8111_lpc.c index 83887b2199..e9bd5fc42b 100644 --- a/src/southbridge/amd/amd8111/amd8111_lpc.c +++ b/src/southbridge/amd/amd8111/amd8111_lpc.c @@ -101,7 +101,7 @@ static void amd8111_lpc_read_resources(device_t dev) IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } diff --git a/src/southbridge/amd/cs5530/cs5530_isa.c b/src/southbridge/amd/cs5530/cs5530_isa.c index c7e8f43f75..ff1617ddc3 100644 --- a/src/southbridge/amd/cs5530/cs5530_isa.c +++ b/src/southbridge/amd/cs5530/cs5530_isa.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <arch/io.h> +#include <arch/ioapic.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -38,7 +39,7 @@ static void cs5530_read_resources(device_t dev) res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } diff --git a/src/southbridge/amd/cs5535/cs5535.c b/src/southbridge/amd/cs5535/cs5535.c index 402362bf1e..42707c049c 100644 --- a/src/southbridge/amd/cs5535/cs5535.c +++ b/src/southbridge/amd/cs5535/cs5535.c @@ -1,5 +1,6 @@ #include <arch/io.h> +#include <arch/ioapic.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> @@ -82,7 +83,7 @@ static void cs5535_read_resources(device_t dev) res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c index c4ceaea4f7..a2ac44647f 100644 --- a/src/southbridge/amd/cs5536/cs5536.c +++ b/src/southbridge/amd/cs5536/cs5536.c @@ -18,6 +18,7 @@ */ #include <arch/io.h> +#include <arch/ioapic.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> @@ -656,7 +657,7 @@ static void cs5536_read_resources(device_t dev) res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } diff --git a/src/southbridge/amd/sb600/sb600_lpc.c b/src/southbridge/amd/sb600/sb600_lpc.c index 67703d15eb..6a17f72318 100644 --- a/src/southbridge/amd/sb600/sb600_lpc.c +++ b/src/southbridge/amd/sb600/sb600_lpc.c @@ -27,6 +27,7 @@ #include <pc80/isa-dma.h> #include <bitops.h> #include <arch/io.h> +#include <arch/ioapic.h> #include "sb600.h" static void lpc_init(device_t dev) @@ -84,7 +85,7 @@ static void sb600_lpc_read_resources(device_t dev) IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; diff --git a/src/southbridge/amd/sb600/sb600_sm.c b/src/southbridge/amd/sb600/sb600_sm.c index 71e546beca..b074edb89e 100644 --- a/src/southbridge/amd/sb600/sb600_sm.c +++ b/src/southbridge/amd/sb600/sb600_sm.c @@ -302,7 +302,7 @@ static void sb600_sm_read_resources(device_t dev) /* apic */ res = new_resource(dev, 0x74); - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 256 * 0x10; res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */ res->align = 8; diff --git a/src/southbridge/amd/sb700/sb700_lpc.c b/src/southbridge/amd/sb700/sb700_lpc.c index f612a6a2df..a3a50c6c9b 100644 --- a/src/southbridge/amd/sb700/sb700_lpc.c +++ b/src/southbridge/amd/sb700/sb700_lpc.c @@ -27,6 +27,7 @@ #include <pc80/isa-dma.h> #include <bitops.h> #include <arch/io.h> +#include <arch/ioapic.h> #include "sb700.h" static void lpc_init(device_t dev) @@ -87,7 +88,7 @@ static void sb700_lpc_read_resources(device_t dev) IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; diff --git a/src/southbridge/amd/sb700/sb700_sm.c b/src/southbridge/amd/sb700/sb700_sm.c index b017a1452f..e700c0b5f3 100644 --- a/src/southbridge/amd/sb700/sb700_sm.c +++ b/src/southbridge/amd/sb700/sb700_sm.c @@ -308,7 +308,7 @@ static void sb700_sm_read_resources(device_t dev) /* apic */ res = new_resource(dev, 0x74); - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 256 * 0x10; res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */ res->align = 8; diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c b/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c index a9fc9994c2..bf70ef323c 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c @@ -13,6 +13,7 @@ #include <pc80/isa-dma.h> #include <bitops.h> #include <arch/io.h> +#include <arch/ioapic.h> #include "bcm5785.h" static void lpc_init(device_t dev) @@ -47,7 +48,7 @@ static void bcm5785_lpc_read_resources(device_t dev) IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } diff --git a/src/southbridge/intel/esb6300/esb6300_lpc.c b/src/southbridge/intel/esb6300/esb6300_lpc.c index 9a48e05303..67bcadc961 100644 --- a/src/southbridge/intel/esb6300/esb6300_lpc.c +++ b/src/southbridge/intel/esb6300/esb6300_lpc.c @@ -242,7 +242,7 @@ static void lpc_init(struct device *dev) value |= (1 << 8)|(1<<7); value |= (6 << 0)|(1<<13)|(1<<11); pci_write_config32(dev, 0xd0, value); - setup_ioapic(0xfec00000, 0); // don't rename IO APIC ID + setup_ioapic(IO_APIC_ADDR, 0); // don't rename IO APIC ID /* disable reset timer */ pci_write_config8(dev, 0xd4, 0x02); @@ -330,7 +330,7 @@ static void esb6300_lpc_read_resources(device_t dev) IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } diff --git a/src/southbridge/intel/esb6300/esb6300_pic.c b/src/southbridge/intel/esb6300/esb6300_pic.c index 5bbf317411..b9bfdf1fe3 100644 --- a/src/southbridge/intel/esb6300/esb6300_pic.c +++ b/src/southbridge/intel/esb6300/esb6300_pic.c @@ -23,7 +23,7 @@ static void pic_init(struct device *dev) pci_write_config8(dev, 0x3c, 0xff); /* Setup the ioapic */ - clear_ioapic(0xfec10000); + clear_ioapic(IO_APIC_ADDR + 0x10000); } static void pic_read_resources(device_t dev) @@ -35,7 +35,7 @@ static void pic_read_resources(device_t dev) /* Report the pic1 mbar resource */ res = new_resource(dev, 0x44); - res->base = 0xfec10000; + res->base = IO_APIC_ADDR + 0x10000; res->size = 256; res->limit = res->base + res->size -1; res->align = 8; diff --git a/src/southbridge/intel/i3100/i3100_lpc.c b/src/southbridge/intel/i3100/i3100_lpc.c index 75cc356179..1544ecd44f 100644 --- a/src/southbridge/intel/i3100/i3100_lpc.c +++ b/src/southbridge/intel/i3100/i3100_lpc.c @@ -372,7 +372,7 @@ static void i3100_lpc_read_resources(device_t dev) IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; diff --git a/src/southbridge/intel/i82371eb/i82371eb_isa.c b/src/southbridge/intel/i82371eb/i82371eb_isa.c index 1f1aef0b93..0cc46a618c 100644 --- a/src/southbridge/intel/i82371eb/i82371eb_isa.c +++ b/src/southbridge/intel/i82371eb/i82371eb_isa.c @@ -25,6 +25,7 @@ #include <device/pci_ids.h> #include <pc80/isa-dma.h> #include <pc80/mc146818rtc.h> +#include <arch/ioapic.h> #include "i82371eb.h" static void isa_init(struct device *dev) @@ -64,7 +65,7 @@ static void sb_read_resources(struct device *dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } diff --git a/src/southbridge/intel/i82801ax/i82801ax_lpc.c b/src/southbridge/intel/i82801ax/i82801ax_lpc.c index 2d03ae870e..46878f8dce 100644 --- a/src/southbridge/intel/i82801ax/i82801ax_lpc.c +++ b/src/southbridge/intel/i82801ax/i82801ax_lpc.c @@ -28,6 +28,7 @@ #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <arch/io.h> +#include <arch/ioapic.h> #include "i82801ax.h" #define GPIO_BASE_ADDR 0x00000500 /* GPIO Base Address Register */ @@ -72,8 +73,8 @@ typedef struct southbridge_intel_i82801ax_config config_t; static void i82801ax_enable_apic(struct device *dev) { u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)0xfec00000; - volatile u32 *ioapic_data = (volatile u32 *)0xfec00010; + volatile u32 *ioapic_index = (volatile u32 *)IO_APIC_ADDR; + volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); /* Set ACPI base address (I/O space). */ pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); @@ -266,7 +267,7 @@ static void i82801ax_lpc_read_resources(device_t dev) IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } diff --git a/src/southbridge/intel/i82801bx/i82801bx_lpc.c b/src/southbridge/intel/i82801bx/i82801bx_lpc.c index 9432d2e788..c379428c86 100644 --- a/src/southbridge/intel/i82801bx/i82801bx_lpc.c +++ b/src/southbridge/intel/i82801bx/i82801bx_lpc.c @@ -28,6 +28,7 @@ #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <arch/io.h> +#include <arch/ioapic.h> #include "i82801bx.h" #define NMI_OFF 0 @@ -74,8 +75,8 @@ typedef struct southbridge_intel_i82801bx_config config_t; static void i82801bx_enable_apic(struct device *dev) { uint32_t reg32; - volatile uint32_t *ioapic_index = (volatile uint32_t *)0xfec00000; - volatile uint32_t *ioapic_data = (volatile uint32_t *)0xfec00010; + volatile uint32_t *ioapic_index = (volatile uint32_t *)IO_APIC_ADDR; + volatile uint32_t *ioapic_data = (volatile uint32_t *)(IO_APIC_ADDR + 0x10); /* Set ACPI base address (I/O space). */ pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); @@ -284,7 +285,7 @@ static void i82801bx_lpc_read_resources(device_t dev) IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } diff --git a/src/southbridge/intel/i82801cx/i82801cx_lpc.c b/src/southbridge/intel/i82801cx/i82801cx_lpc.c index 3720262f05..2f2c4600a2 100644 --- a/src/southbridge/intel/i82801cx/i82801cx_lpc.c +++ b/src/southbridge/intel/i82801cx/i82801cx_lpc.c @@ -11,6 +11,7 @@ #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <arch/io.h> +#include <arch/ioapic.h> #include "i82801cx.h" #define NMI_OFF 0 @@ -26,8 +27,8 @@ static void i82801cx_enable_ioapic( struct device *dev) { uint32_t dword; - volatile uint32_t* ioapic_index = (volatile uint32_t*)0xfec00000; - volatile uint32_t* ioapic_data = (volatile uint32_t*)0xfec00010; + volatile uint32_t* ioapic_index = (volatile uint32_t*)IO_APIC_ADDR; + volatile uint32_t* ioapic_data = (volatile uint32_t*)(IO_APIC_ADDR + 0x10); dword = pci_read_config32(dev, GEN_CNTL); dword |= (3 << 7); /* enable ioapic & disable SMBus interrupts */ @@ -224,7 +225,7 @@ static void i82801cx_lpc_read_resources(device_t dev) IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index cbdbc963af..a38c793eda 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -36,8 +36,6 @@ extern void i82801dx_enable(device_t dev); #endif -#define IO_APIC_ADDR 0xfec00000 - /* * HPET Memory Address Range. Possible values: * 0xfed00000 for FED0_0000h - FED0_03FFh diff --git a/src/southbridge/intel/i82801dx/i82801dx_lpc.c b/src/southbridge/intel/i82801dx/i82801dx_lpc.c index 0bba26a82f..768e70096b 100644 --- a/src/southbridge/intel/i82801dx/i82801dx_lpc.c +++ b/src/southbridge/intel/i82801dx/i82801dx_lpc.c @@ -29,6 +29,7 @@ #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <arch/io.h> +#include <arch/ioapic.h> #include "i82801dx.h" #define NMI_OFF 0 @@ -317,7 +318,7 @@ static void i82801dx_lpc_read_resources(device_t dev) IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } diff --git a/src/southbridge/intel/i82801ex/i82801ex_lpc.c b/src/southbridge/intel/i82801ex/i82801ex_lpc.c index df05cc85b7..998360ce07 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_lpc.c +++ b/src/southbridge/intel/i82801ex/i82801ex_lpc.c @@ -314,7 +314,7 @@ static void i82801ex_lpc_read_resources(device_t dev) IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 559c896901..f6a54e94d5 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -32,7 +32,6 @@ #define DEFAULT_GPIOBASE 0x0480 #define DEFAULT_PMBASE 0x0500 -#define IO_APIC_ADDR 0xfec00000 #define HPET_ADDR 0xfed00000 #define DEFAULT_RCBA 0xfed1c000 diff --git a/src/southbridge/intel/i82801gx/i82801gx_lpc.c b/src/southbridge/intel/i82801gx/i82801gx_lpc.c index d0e076730c..f486c1ebf8 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_lpc.c +++ b/src/southbridge/intel/i82801gx/i82801gx_lpc.c @@ -26,6 +26,7 @@ #include <pc80/isa-dma.h> #include <pc80/i8259.h> #include <arch/io.h> +#include <arch/ioapic.h> #include "i82801gx.h" #define NMI_OFF 0 @@ -476,7 +477,7 @@ static void i82801gx_lpc_read_resources(device_t dev) IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } diff --git a/src/southbridge/nvidia/ck804/ck804_lpc.c b/src/southbridge/nvidia/ck804/ck804_lpc.c index 7037d9e2da..7d8c9ad723 100644 --- a/src/southbridge/nvidia/ck804/ck804_lpc.c +++ b/src/southbridge/nvidia/ck804/ck804_lpc.c @@ -211,7 +211,7 @@ static void ck804_lpc_read_resources(device_t dev) IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } diff --git a/src/southbridge/nvidia/mcp55/mcp55_lpc.c b/src/southbridge/nvidia/mcp55/mcp55_lpc.c index 040ab62273..0fb77c3e38 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_lpc.c +++ b/src/southbridge/nvidia/mcp55/mcp55_lpc.c @@ -185,7 +185,7 @@ static void mcp55_lpc_read_resources(device_t dev) IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } diff --git a/src/southbridge/sis/sis966/sis966_lpc.c b/src/southbridge/sis/sis966/sis966_lpc.c index b987b4318d..c6a1fce20d 100644 --- a/src/southbridge/sis/sis966/sis966_lpc.c +++ b/src/southbridge/sis/sis966/sis966_lpc.c @@ -178,7 +178,7 @@ static void sis966_lpc_read_resources(device_t dev) IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } diff --git a/src/southbridge/via/vt8231/vt8231_lpc.c b/src/southbridge/via/vt8231/vt8231_lpc.c index fadbcf2fb7..a063adf710 100644 --- a/src/southbridge/via/vt8231/vt8231_lpc.c +++ b/src/southbridge/via/vt8231/vt8231_lpc.c @@ -3,9 +3,8 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <device/pci_ids.h> - #include <pc80/mc146818rtc.h> - +#include <arch/ioapic.h> #include "chip.h" /* PIRQ init @@ -141,7 +140,7 @@ static void vt8231_read_resources(device_t dev) res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } diff --git a/src/southbridge/via/vt8235/vt8235_lpc.c b/src/southbridge/via/vt8235/vt8235_lpc.c index 15ff5392b2..b355ad0d88 100644 --- a/src/southbridge/via/vt8235/vt8235_lpc.c +++ b/src/southbridge/via/vt8235/vt8235_lpc.c @@ -4,9 +4,8 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <device/pci_ids.h> - #include <pc80/mc146818rtc.h> - +#include <arch/ioapic.h> #include "chip.h" /* The epia-m is really short on interrupts available, so PCI interupts A & D are ganged togther and so are B & C. @@ -228,7 +227,7 @@ static void vt8235_read_resources(device_t dev) res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } diff --git a/src/southbridge/via/vt8237r/vt8237r.h b/src/southbridge/via/vt8237r/vt8237r.h index d54c533aee..ba7089b414 100644 --- a/src/southbridge/via/vt8237r/vt8237r.h +++ b/src/southbridge/via/vt8237r/vt8237r.h @@ -35,7 +35,6 @@ #define VT8237S_SPI_MEM_BASE 0xfed02000UL #endif #define VT8237R_HPET_ADDR 0xfed00000ULL -#define VT8237R_APIC_BASE 0xfec00000ULL /* IDE */ #define IDE_CS 0x40 diff --git a/src/southbridge/via/vt8237r/vt8237r_lpc.c b/src/southbridge/via/vt8237r/vt8237r_lpc.c index 3074bc8c3c..2de64f03ce 100644 --- a/src/southbridge/via/vt8237r/vt8237r_lpc.c +++ b/src/southbridge/via/vt8237r/vt8237r_lpc.c @@ -490,7 +490,7 @@ static void vt8237r_read_resources(device_t dev) /* Fixed APIC resource */ res = new_resource(dev, 0x44); - res->base = VT8237R_APIC_BASE; + res->base = IO_APIC_ADDR; res->size = 256; res->limit = 0xffffffffUL; res->align = 8; @@ -516,7 +516,7 @@ static void southbridge_init_common(struct device *dev) { vt8237_common_init(dev); pci_routing_fixup(dev); - setup_ioapic(VT8237R_APIC_BASE, VT8237R_APIC_ID); + setup_ioapic(IO_APIC_ADDR, VT8237R_APIC_ID); setup_i8259(); init_keyboard(dev); } |