diff options
| author | Stefan Reinauer <reinauer@chromium.org> | 2013-10-07 16:29:54 -0700 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2014-07-05 10:12:05 +0200 |
| commit | 779e178353a1adb6e6bee8fcad688bcbceb172cf (patch) | |
| tree | 62a09c0057d250fbe455b9a8aa8d53700d9d369d /src/southbridge | |
| parent | c50c0ab4566a031a0420d762f2403126635bba93 (diff) | |
| download | coreboot-779e178353a1adb6e6bee8fcad688bcbceb172cf.tar.xz | |
intel/lynxpoint: Export pch_enable_lpc() for Super I/O systems
In order to enable a Super I/O in non Chrome EC systems we
need to make pch_enable_lpc() available to the mainboard
romstage.c
BUG=none
BRANCH=none
TEST=boot ChromeOS on Beltino
Change-Id: I34e7d23012e1852c69e82ba7cdc81a05751846de
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172180
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/6019
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/early_pch.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pch.h | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 9909bb6d44..fdbb2a3d47 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -102,7 +102,7 @@ static int sleep_type_s3(void) return is_s3; } -static void pch_enable_lpc(void) +void pch_enable_lpc(void) { const struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); const struct southbridge_intel_lynxpoint_config *config = NULL; diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 339636742b..9b5cb6f160 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -213,6 +213,7 @@ int smbus_read_byte(unsigned device, unsigned address); int early_spi_read(u32 offset, u32 size, u8 *buffer); int early_pch_init(const void *gpio_map, const struct rcba_config_instruction *rcba_config); +void pch_enable_lpc(void); #endif /* !__PRE_RAM__ && !__SMM__ */ #endif /* __ASSEMBLER__ */ |