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| author | Paul Menzel <paulepanter@users.sourceforge.net> | 2013-04-23 13:00:34 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-05-03 06:26:28 +0200 |
| commit | ac222273701cc6d648d4362093762124662572c3 (patch) | |
| tree | b9c50c02d95e177f752f0a94c53329717e265625 /src/southbridge | |
| parent | e62b8e9a8fb08d4afd88ec57414a33b7154aaa67 (diff) | |
| download | coreboot-ac222273701cc6d648d4362093762124662572c3.tar.xz | |
Intel Lynx Point: Use 2 << 24 to clarify that I/O APIC ID is 2
Commit »haswell: Add initial support for Haswell platforms« (76c3700f)
[1] used `1 << 25` to set the I/O APIC ID of 2. Instead using
`2 << 24`, which is the same value, makes it clear, that the
I/O APIC ID is 2.
Commit »Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID
is 2« (8c937c7e) [2] is used as a template.
[1] http://review.coreboot.org/2616
[2] http://review.coreboot.org/3100
Change-Id: I28f9e90856157b4fdd9a1e781472cc4f51d25ece
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3123
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/lpc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index f6c64c56a0..40e04683ae 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -56,7 +56,7 @@ static void pch_enable_apic(struct device *dev) pci_write_config8(dev, ACPI_CNTL, 0x80); *ioapic_index = 0; - *ioapic_data = (1 << 25); + *ioapic_data = (2 << 24); /* affirm full set of redirection table entries ("write once") */ *ioapic_index = 1; |