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authorKyösti Mälkki <kyosti.malkki@gmail.com>2020-06-17 10:34:26 +0300
committerPatrick Georgi <pgeorgi@google.com>2020-06-24 11:49:15 +0000
commitc3c55210ee598e2dfcfc0bbe664cd703e6fdf3fe (patch)
tree8efb929b92a7c8cfd7cb92042ac628d396e3d6ae /src/southbridge
parent5daa1d38985a19dc84f2299dba2e340dda2870ae (diff)
downloadcoreboot-c3c55210ee598e2dfcfc0bbe664cd703e6fdf3fe.tar.xz
ACPI: Replace smm_setup_structures()
Except for whitespace and varying casts the codes were the same when implemented. Platforms that did not implement this are tagged with ACPI_NO_SMI_GNVS. Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/agesa/hudson/smi.c5
-rw-r--r--src/southbridge/amd/pi/hudson/smi.c5
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c2
-rw-r--r--src/southbridge/intel/common/smi.c19
-rw-r--r--src/southbridge/intel/i82801gx/lpc.c2
-rw-r--r--src/southbridge/intel/i82801ix/lpc.c2
-rw-r--r--src/southbridge/intel/i82801jx/lpc.c2
-rw-r--r--src/southbridge/intel/ibexpeak/lpc.c2
-rw-r--r--src/southbridge/intel/lynxpoint/lpc.c2
-rw-r--r--src/southbridge/intel/lynxpoint/smi.c19
10 files changed, 6 insertions, 54 deletions
diff --git a/src/southbridge/amd/agesa/hudson/smi.c b/src/southbridge/amd/agesa/hudson/smi.c
index 6c7682511b..f54faeb27d 100644
--- a/src/southbridge/amd/agesa/hudson/smi.c
+++ b/src/southbridge/amd/agesa/hudson/smi.c
@@ -10,11 +10,6 @@
#include "smi.h"
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
-{
- printk(BIOS_DEBUG, "%s STUB!!!\n", __func__);
-}
-
/** Set the EOS bit and enable SMI generation from southbridge */
void global_smi_enable(void)
{
diff --git a/src/southbridge/amd/pi/hudson/smi.c b/src/southbridge/amd/pi/hudson/smi.c
index 6c7682511b..f54faeb27d 100644
--- a/src/southbridge/amd/pi/hudson/smi.c
+++ b/src/southbridge/amd/pi/hudson/smi.c
@@ -10,11 +10,6 @@
#include "smi.h"
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
-{
- printk(BIOS_DEBUG, "%s STUB!!!\n", __func__);
-}
-
/** Set the EOS bit and enable SMI generation from southbridge */
void global_smi_enable(void)
{
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 038bb37c61..fb822462bb 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -665,7 +665,7 @@ static void southbridge_inject_dsdt(const struct device *dev)
#endif
/* And tell SMI about it */
- smm_setup_structures(gnvs, NULL, NULL);
+ apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to DSDT. */
acpigen_write_scope("\\");
diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c
index 913cce0cfa..06d7c74e58 100644
--- a/src/southbridge/intel/common/smi.c
+++ b/src/southbridge/intel/common/smi.c
@@ -79,25 +79,6 @@ void global_smi_enable(void)
smm_southbridge_enable(PWRBTN_EN | GBL_EN);
}
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
-{
- /*
- * Issue SMI to set the gnvs pointer in SMM.
- * tcg and smi1 are unused.
- *
- * EAX = APM_CNT_GNVS_UPDATE
- * EBX = gnvs pointer
- * EDX = APM_CNT
- */
- asm volatile (
- "outb %%al, %%dx\n\t"
- : /* ignore result */
- : "a" (APM_CNT_GNVS_UPDATE),
- "b" ((uintptr_t)gnvs),
- "d" (APM_CNT)
- );
-}
-
void smm_southbridge_clear_state(void)
{
if (smi_enabled())
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 88c5633ffb..55f3a84ed5 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -622,7 +622,7 @@ static void southbridge_inject_dsdt(const struct device *dev)
acpi_create_gnvs(gnvs);
/* And tell SMI about it */
- smm_setup_structures(gnvs, NULL, NULL);
+ apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to SSDT. */
acpigen_write_scope("\\");
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index 27a7c959c9..db214ee7a8 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -464,7 +464,7 @@ static void southbridge_inject_dsdt(const struct device *dev)
acpi_create_gnvs(gnvs);
/* And tell SMI about it */
- smm_setup_structures(gnvs, NULL, NULL);
+ apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to SSDT. */
acpigen_write_scope("\\");
diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c
index edd1430ab3..0a2440da12 100644
--- a/src/southbridge/intel/i82801jx/lpc.c
+++ b/src/southbridge/intel/i82801jx/lpc.c
@@ -623,7 +623,7 @@ static void southbridge_inject_dsdt(const struct device *dev)
acpi_create_gnvs(gnvs);
/* And tell SMI about it */
- smm_setup_structures(gnvs, NULL, NULL);
+ apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to SSDT. */
acpigen_write_scope("\\");
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 4f86e9b80b..5a6483f58c 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -566,7 +566,7 @@ static void southbridge_inject_dsdt(const struct device *dev)
gnvs->pcnt = dev_count_cpu();
/* And tell SMI about it */
- smm_setup_structures(gnvs, NULL, NULL);
+ apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to SSDT. */
acpigen_write_scope("\\");
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 6cdbc78212..4b12b3278c 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -721,7 +721,7 @@ static void southbridge_inject_dsdt(const struct device *dev)
gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
/* And tell SMI about it */
- smm_setup_structures(gnvs, NULL, NULL);
+ apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to DSDT. */
acpigen_write_scope("\\");
diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c
index 48b76e282a..6edf5c1836 100644
--- a/src/southbridge/intel/lynxpoint/smi.c
+++ b/src/southbridge/intel/lynxpoint/smi.c
@@ -57,22 +57,3 @@ void global_smi_enable(void)
{
smm_southbridge_enable(PWRBTN_EN | GBL_EN);
}
-
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
-{
- /*
- * Issue SMI to set the gnvs pointer in SMM.
- * tcg and smi1 are unused.
- *
- * EAX = APM_CNT_GNVS_UPDATE
- * EBX = gnvs pointer
- * EDX = APM_CNT
- */
- asm volatile (
- "outb %%al, %%dx\n\t"
- : /* ignore result */
- : "a" (APM_CNT_GNVS_UPDATE),
- "b" ((u32)gnvs),
- "d" (APM_CNT)
- );
-}