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authorKeith Hui <buurin@gmail.com>2020-01-11 03:49:17 -0500
committerPatrick Georgi <pgeorgi@google.com>2020-03-03 07:36:53 +0000
commitce622389983f941f5b86907c41c9c843fadccce0 (patch)
tree78f721aa625ed177ae36b6c94915ddd00e475ea3 /src/southbridge
parent7af59f709a89d20c1691d1a7316b136c7024aaf9 (diff)
downloadcoreboot-ce622389983f941f5b86907c41c9c843fadccce0.tar.xz
sb/intel/i82371eb: Support reconfiguring GPO22/23
XOE# and XDIR# can be used as GPOs 23/22 if X-Bus functionality is not required. Turns out asus/p2b-ls is using them to control termination for the onboard SCSI buses. Add support to allow this reconfiguration. Change-Id: I2dab6fafbd67a98ed1cac1ffcf9352be4a87c3e9 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/i82371eb/chip.h3
-rw-r--r--src/southbridge/intel/i82371eb/isa.c7
2 files changed, 9 insertions, 1 deletions
diff --git a/src/southbridge/intel/i82371eb/chip.h b/src/southbridge/intel/i82371eb/chip.h
index 28975a2bbb..986208208e 100644
--- a/src/southbridge/intel/i82371eb/chip.h
+++ b/src/southbridge/intel/i82371eb/chip.h
@@ -28,6 +28,9 @@ struct southbridge_intel_i82371eb_config {
int ide1_drive1_udma33_enable:1;
int ide_legacy_enable:1;
int usb_enable:1;
+ int gpo22_enable:1; /* GPO22/GPO23 (1) vs. XDIR#/XOE# (0) */
+ int gpo22:1;
+ int gpo23:1;
/* acpi */
u32 gpo; /* gpio output default */
u8 lid_polarity;
diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c
index bb88f7ddc0..a57d61ae03 100644
--- a/src/southbridge/intel/i82371eb/isa.c
+++ b/src/southbridge/intel/i82371eb/isa.c
@@ -28,6 +28,7 @@
#include <arch/acpigen.h>
#endif
#include "i82371eb.h"
+#include "chip.h"
#if CONFIG(IOAPIC)
static void enable_intel_82093aa_ioapic(void)
@@ -63,6 +64,7 @@ static void enable_intel_82093aa_ioapic(void)
static void isa_init(struct device *dev)
{
u32 reg32;
+ struct southbridge_intel_i82371eb_config *sb = dev->chip_info;
/* Initialize the real time clock (RTC). */
cmos_init(0);
@@ -80,7 +82,10 @@ static void isa_init(struct device *dev)
*/
reg32 = pci_read_config32(dev, GENCFG);
reg32 |= ISA; /* Select ISA, not EIO. */
- pci_write_config16(dev, GENCFG, reg32);
+
+ /* Some boards use GPO22/23. Select it if configured. */
+ reg32 = ONOFF(sb->gpo22_enable, reg32, GPO2223);
+ pci_write_config32(dev, GENCFG, reg32);
/* Initialize ISA DMA. */
isa_dma_init();