This patch converts the Geode GX2 boards to CAR.

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Joseph Smith <joe@settoplinux.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5669 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

5 files changed, 149 insertions, 220 deletions

diff --git a/src/southbridge/amd/cs5535/chipsetinit.c b/src/southbridge/amd/cs5535/chipsetinit.c
index d31efd3e52..9fae6037ba 100644
--- a/src/southbridge/amd/cs5535/chipsetinit.c
+++ b/src/southbridge/amd/cs5535/chipsetinit.c
@@ -13,8 +13,6 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/cache.h>
 #include "southbridge/amd/cs5535/cs5535.h"
-// This code uses some cs5536 includes because cs5535 includes are empty:
-#include "southbridge/amd/cs5536/cs5536.h"
 
 /* the structs in this file only set msr.lo. But ... that may not always be true */
 
diff --git a/src/southbridge/amd/cs5535/cs5535.h b/src/southbridge/amd/cs5535/cs5535.h
index 82d657204a..16a319804c 100644
--- a/src/southbridge/amd/cs5535/cs5535.h
+++ b/src/southbridge/amd/cs5535/cs5535.h
@@ -1,4 +1,125 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Nils Jacobs
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
 #ifndef _CS5535_H
 #define _CS5535_H
 
+/*	SouthBridge Equates */
+#define CS5535_GLINK_PORT_NUM	0x02	/* port of the SouthBridge */
+#define NB_PCI			((2	<< 29) + (4 << 26))	/* NB GLPCI is in the same location on all Geodes. */
+#define MSR_SB			((CS5535_GLINK_PORT_NUM << 23) + NB_PCI)	/* address to the SouthBridge */
+#define SB_SHIFT		20	/* 29 -> 26 -> 23 -> 20...... When making a SB address uses this shift. */
+
+#define CS5535_DEV_NUM 		0x0F	/* default PCI device number for CS5535 */
+#define SMBUS_IO_BASE		0x6000
+#define GPIO_IO_BASE		0x6100
+#define MFGPT_IO_BASE		0x6200
+#define ACPI_IO_BASE		0x9C00
+#define PMS_IO_BASE		0x9D00
+
+/* Cs5536 as follows. */
+/*	SB_GLIU */
+/*	port0 - GLIU */
+/*	port1 - GLPCI */
+/*	port2 - USB Controller #2 */
+/*	port3 - ATA-5 Controller */
+/*	port4 - MDD */
+/*	port5 - AC97 */
+/*	port6 - USB Controller #1 */
+/*	port7 - GLCP */
+
+#define MSR_SB_GLIU		((9 << 14) + MSR_SB)		/* 51024xxx or 510*xxxx - fake out just like GL0 on CPU. */
+#define MSR_SB_GLPCI		(MSR_SB)			/* 5100xxxx - don't go to the GLIU */
+#define MSR_SB_USB2		((2 << SB_SHIFT) + MSR_SB)	/* 5120xxxx */
+#define MSR_SB_ATA		((3 << SB_SHIFT) + MSR_SB)	/* 5130xxxx */
+#define MSR_SB_MDD		((4 << SB_SHIFT) + MSR_SB)	/* 5140xxxx, a.k.a. DIVIL = Diverse Integrated Logic device */
+#define MSR_SB_AC97		((5 << SB_SHIFT) + MSR_SB)	/* 5150xxxx */
+#define MSR_SB_USB1		((6 << SB_SHIFT) + MSR_SB)	/* 5160xxxx */
+#define MSR_SB_GLCP		((7 << SB_SHIFT) + MSR_SB)	/* 5170xxxx */
+
+/* GLIU */
+#define GLIU_SB_GLD_MSR_PM	(MSR_SB_GLIU + 0x04)
+
+/* USB1 */
+#define USB1_SB_GLD_MSR_CONF	(MSR_SB_USB1 + 0x01)
+#define USB1_SB_GLD_MSR_PM	(MSR_SB_USB1 + 0x04)
+
+/* USB2 */
+#define USB2_SB_GLD_MSR_CONF	(MSR_SB_USB2 + 0x01)
+#define USB2_SB_GLD_MSR_PM	(MSR_SB_USB2 + 0x04)
+
+/* ATA */
+#define ATA_SB_GLD_MSR_CONF	(MSR_SB_ATA + 0x01)
+#define ATA_SB_GLD_MSR_ERR	(MSR_SB_ATA + 0x03)
+#define ATA_SB_GLD_MSR_PM	(MSR_SB_ATA + 0x04)
+
+/* AC97 */
+#define AC97_SB_GLD_MSR_CONF	(MSR_SB_AC97 + 0x01)
+#define AC97_SB_GLD_MSR_PM	(MSR_SB_AC97 + 0x04)
+
+/* GLPCI */
+#define GLPCI_SB_GLD_MSR_PM	(MSR_SB_GLPCI + 0x04)
+#define GLPCI_SB_CTRL		(MSR_SB_GLPCI + 0x10)
+#define GLPCI_CRTL_PPIDE_SET	(1 << 17)
+
+/* GLCP */
+#define GLCP_SB_GLD_MSR_PM	(MSR_SB_GLCP + 0x04)
+
+/* MDD */
+#define MDD_SB_GLD_MSR_CONF	(MSR_SB_MDD + 0x01)
+#define MDD_SB_GLD_MSR_PM	(MSR_SB_MDD + 0x04)
+#define MDD_LBAR_SMB		(MSR_SB_MDD + 0x0B)
+#define MDD_LBAR_GPIO		(MSR_SB_MDD + 0x0C)
+#define MDD_LBAR_MFGPT		(MSR_SB_MDD + 0x0D)
+#define MDD_LBAR_ACPI		(MSR_SB_MDD + 0x0E)
+#define MDD_LBAR_PMS		(MSR_SB_MDD + 0x0F)
+#define MDD_LBAR_FLSH0		(MSR_SB_MDD + 0x010)
+#define MDD_LBAR_FLSH1		(MSR_SB_MDD + 0x011)
+#define MDD_LBAR_FLSH2		(MSR_SB_MDD + 0x012)
+#define MDD_LBAR_FLSH3		(MSR_SB_MDD + 0x013)
+#define MDD_PIN_OPT		(MSR_SB_MDD + 0x015)
+#define MDD_NORF_CNTRL		(MSR_SB_MDD + 0x018)
+
+/* GPIO */
+#define GPIOL_2_SET		(1 << 2)
+
+/* GPIO LOW Bank Bit Registers */
+#define GPIOL_INPUT_ENABLE	(0x20)
+#define GPIOL_IN_AUX1_SELECT	(0x34)
+
+/* FLASH device macros */
+#define FLASH_TYPE_NONE		0	/* No flash device installed */
+#define FLASH_TYPE_NAND 	1	/* NAND device */
+
+#define FLASH_IF_MEM		1	/* Memory or memory-mapped I/O interface for Flash device */
+
+/* Flash Memory Mask values */
+#define FLASH_MEM_4K		0xFFFFF000
+
+#if !defined(ASSEMBLY) && !defined(__ROMCC__)
+#if defined(__PRE_RAM__)
+void cs5535_disable_internal_uart(void);
+#else
+void chipsetinit(void);
 #endif
+#endif
+
+#endif				/* _CS5535_H */
diff --git a/src/southbridge/amd/cs5535/cs5535_early_setup.c b/src/southbridge/amd/cs5535/cs5535_early_setup.c
index 91dc852012..1a612cc55f 100644
--- a/src/southbridge/amd/cs5535/cs5535_early_setup.c
+++ b/src/southbridge/amd/cs5535/cs5535_early_setup.c
@@ -8,9 +8,6 @@
  *
  */
 
-#define CS5535_GLINK_PORT_NUM	0x02	/* the geode link port number to the CS5535 */
-#define CS5535_DEV_NUM 		0x0F	/* default PCI device number for CS5535 */
-
 /**
  * @brief Setup PCI IDSEL for CS5535
  *
@@ -51,46 +48,33 @@ static void cs5535_usb_swapsif(void)
 	}
 }
 
-static int cs5535_setup_iobase(void)
+static void cs5535_setup_iobase(void)
 {
 	msr_t msr;
-
 	/* setup LBAR for SMBus controller */
-	__builtin_wrmsr(0x5140000b, 0x00006000, 0x0000f001);
+	msr.hi = 0x0000f001;
+	msr.lo = SMBUS_IO_BASE;
+	wrmsr(MDD_LBAR_SMB, msr);
+
 	/* setup LBAR for GPIO */
-	__builtin_wrmsr(0x5140000c, 0x00006100, 0x0000f001);
+	msr.hi = 0x0000f001;
+	msr.lo = GPIO_IO_BASE;
+	wrmsr(MDD_LBAR_GPIO, msr);
+
 	/* setup LBAR for MFGPT */
-	__builtin_wrmsr(0x5140000d, 0x00006200, 0x0000f001);
-	/* setup LBAR for ACPI */
-	__builtin_wrmsr(0x5140000e, 0x00009c00, 0x0000f001);
-	/* setup LBAR for PM Support */
-	__builtin_wrmsr(0x5140000f, 0x00009d00, 0x0000f001);
-}
+	msr.hi = 0x0000f001;
+	msr.lo = MFGPT_IO_BASE;
+	wrmsr(MDD_LBAR_MFGPT, msr);
 
-static void cs5535_setup_power_bottun(void)
-{
-	/* not implemented yet */
-#if 0
-	pwrBtn_setup:
-	;
-	;	Power Button Setup
-	;
-	;mov	eax, 0C0020000h				; 4 seconds + lock
-	mov	eax, 040020000h				; 4 seconds no lock
-	mov	dx, PMLogic_BASE + 40h
-	out	dx, eax
-
-	; setup GPIO24, it is the external signal for 5535 vsb_work_aux
-	; which controls all voltage rails except Vstandby & Vmem.
-	; We need to enable, OUT_AUX1 and OUTPUT_ENABLE in this order.
-	; If GPIO24 is not enabled then soft-off will not work.
-	mov	dx, GPIOH_OUT_AUX1_SELECT
-	mov	eax, GPIOH_24_SET
-	out	dx, eax
-	mov	dx, GPIOH_OUTPUT_ENABLE
-	out	dx, eax
+	/* setup LBAR for ACPI */
+	msr.hi = 0x0000f001;
+	msr.lo = ACPI_IO_BASE;
+	wrmsr(MDD_LBAR_ACPI, msr);
 
-#endif
+	/* setup LBAR for PM Support */
+	msr.hi = 0x0000f001;
+	msr.lo = PMS_IO_BASE;
+	wrmsr(MDD_LBAR_PMS, msr);
 }
 
 static void cs5535_setup_gpio(void)
@@ -115,27 +99,8 @@ static void cs5535_setup_gpio(void)
 	//outl(val, 0x6100 + 0x34);
 }
 
-static void cs5535_disable_internal_uart(void)
+void cs5535_disable_internal_uart(void)
 {
-	/* not implemented yet */
-#if 0
-	; The UARTs default to enabled.
-	; Disable and reset them and configure them later. (SIO init)
-	mov	ecx, MDD_UART1_CONF
-	RDMSR
-	mov	eax, 1h					; reset
-	WRMSR
-	mov	eax, 0h					; disabled
-	WRMSR
-
-	mov	ecx, MDD_UART2_CONF
-	RDMSR
-	mov	eax, 1h					; reset
-	WRMSR
-	mov	eax, 0h					; disabled
-	WRMSR
-
-#endif
 }
 
 static void cs5535_setup_cis_mode(void)
@@ -143,19 +108,21 @@ static void cs5535_setup_cis_mode(void)
 	msr_t msr;
 
 	/* setup CPU interface serial to mode C on both sides */
-	msr = __builtin_rdmsr(0x51000010);
+	msr = rdmsr(GLPCI_SB_CTRL);
 	msr.lo &= ~0x18;
 	msr.lo |= 0x10;
-	__builtin_wrmsr(0x51000010, msr.lo, msr.hi);
+	wrmsr(GLPCI_SB_CTRL, msr);
 	//Only do this if we are building for 5535
-	__builtin_wrmsr(0x54002010, 0x00000002, 0x00000000);
+	msr.lo = 0x2;
+	msr.hi = 0x0;
+	wrmsr(VIP_GIO_MSR_SEL, msr);
 }
 
 static void dummy(void)
 {
 }
 
-static int cs5535_early_setup(void)
+static void cs5535_early_setup(void)
 {
 	msr_t msr;
 
diff --git a/src/southbridge/amd/cs5535/cs5535_early_smbus.c b/src/southbridge/amd/cs5535/cs5535_early_smbus.c
index ec801f02a8..0aab46f6a3 100644
--- a/src/southbridge/amd/cs5535/cs5535_early_smbus.c
+++ b/src/southbridge/amd/cs5535/cs5535_early_smbus.c
@@ -3,7 +3,7 @@
 #define SMBUS_IO_BASE 0x6000
 
 /* initialization for SMBus Controller */
-static int cs5535_enable_smbus(void)
+static void cs5535_enable_smbus(void)
 {
 	unsigned char val;
 
@@ -20,26 +20,3 @@ static int cs5535_enable_smbus(void)
 	val |= (0xEF | SMB_ADD_SAEN);
 	outb(val, SMBUS_IO_BASE + SMB_ADD);
 }
-
-static int smbus_read_byte(unsigned device, unsigned address)
-{
-        return do_smbus_read_byte(SMBUS_IO_BASE, device, address-1);
-}
-
-#if 0
-static int smbus_recv_byte(unsigned device)
-{
-        return do_smbus_recv_byte(SMBUS_IO_BASE, device);
-}
-
-static int smbus_send_byte(unsigned device, unsigned char val)
-{
-        return do_smbus_send_byte(SMBUS_IO_BASE, device, val);
-}
-
-
-static int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
-{
-        return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
-}
-#endif
diff --git a/src/southbridge/amd/cs5535/cs5535_smbus.h b/src/southbridge/amd/cs5535/cs5535_smbus.h
index 799e226f5e..db35f6ee7b 100644
--- a/src/southbridge/amd/cs5535/cs5535_smbus.h
+++ b/src/southbridge/amd/cs5535/cs5535_smbus.h
@@ -44,137 +44,3 @@
 #define SMBUS_STATUS_MASK 0xfbff
 
 #define SMBUS_IO_BASE 0x6000
-
-static void smbus_delay(void)
-{
-    	outb(0x80, 0x80);
-}
-
-/* generate a smbus start condition */
-static int smbus_start_condition(unsigned smbus_io_base)
-{
-	unsigned char val;
-	unsigned long loops;
-	loops = SMBUS_TIMEOUT;
-
-	/* issue a START condition */
-	val = inb(smbus_io_base + SMB_CTRL1);
-	outb(val | SMB_CTRL1_START, smbus_io_base + SMB_CTRL1);
-
-	/* check for bus conflict */
-	val = inb(smbus_io_base + SMB_STS);
-	if ((val & SMB_STS_BER) != 0)
-		return SMBUS_ERROR;
-
-	/* check for SDA status */
-	do {
-		smbus_delay();
-		val = inw(smbus_io_base + SMB_STS);
-		if ((val & SMB_STS_SDAST) != 0) {
-			break;
-		}
-	} while(--loops);
-	return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
-}
-
-static int smbus_check_stop_condition(unsigned smbus_io_base)
-{
-	unsigned char val;
-	unsigned long loops;
-	loops = SMBUS_TIMEOUT;
-	/* check for SDA status */
-	do {
-		smbus_delay();
-		val = inw(smbus_io_base + SMB_CTRL1);
-		if ((val & SMB_CTRL1_STOP) == 0) {
-			break;
-		}
-	} while(--loops);
-	return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
-}
-
-static int smbus_stop_condition(unsigned smbus_io_base)
-{
-	unsigned char val;
-	val = inb(smbus_io_base + SMB_CTRL1);
-	outb(SMB_CTRL1_STOP, smbus_io_base + SMB_CTRL1);
-}
-
-static int smbus_send_slave_address(unsigned smbus_io_base, unsigned char device)
-{
-	unsigned char val;
-	unsigned long loops;
-	loops = SMBUS_TIMEOUT;
-
-	/* send the slave address */
-	outb(device, smbus_io_base + SMB_SDA);
-
-	/* check for bus conflict and NACK */
-	val = inb(smbus_io_base + SMB_STS);
-	if (((val & SMB_STS_BER)    != 0) ||
-	    ((val & SMB_STS_NEGACK) != 0))
-		return SMBUS_ERROR;
-
-	/* check for SDA status */
-	do {
-		smbus_delay();
-		val = inw(smbus_io_base + SMB_STS);
-		if ((val & SMB_STS_SDAST) != 0) {
-			break;
-		}
-	} while(--loops);
-	return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
-}
-
-static int smbus_send_command(unsigned smbus_io_base, unsigned char command)
-{
-        unsigned char val;
-	unsigned long loops;
-	loops = SMBUS_TIMEOUT;
-
-	/* send the command */
-	outb(command, smbus_io_base + SMB_SDA);
-
-	/* check for bus conflict and NACK */
-	val = inb(smbus_io_base + SMB_STS);
-	if (((val & SMB_STS_BER)    != 0) ||
-	    ((val & SMB_STS_NEGACK) != 0))
-		return SMBUS_ERROR;
-
-	/* check for SDA status */
-	do {
-		smbus_delay();
-		val = inw(smbus_io_base + SMB_STS);
-		if ((val & SMB_STS_SDAST) != 0) {
-			break;
-		}
-	} while(--loops);
-	return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
-}
-
-static unsigned char do_smbus_read_byte(unsigned smbus_io_base, unsigned char device, unsigned char address)
-{
-	unsigned char val, val1;
-
-	smbus_check_stop_condition(smbus_io_base);
-
-	smbus_start_condition(smbus_io_base);
-
-	smbus_send_slave_address(smbus_io_base, device);
-
-	smbus_send_command(smbus_io_base, address);
-
-	smbus_start_condition(smbus_io_base);
-
-	smbus_send_slave_address(smbus_io_base, device | 0x01);
-
-	/* send NACK to slave */
-	val = inb(smbus_io_base + SMB_CTRL1);
-	outb(val | SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
-
-	val = inb(smbus_io_base + SMB_SDA);
-
-	//smbus_stop_condition(smbus_io_base);
-
-	return val;
-}