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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-04-23 22:14:50 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-04-25 15:54:35 +0000 |
| commit | f4ed5dc7f47b465707170c2ad9bab11826dea12c (patch) | |
| tree | 2e02d93a74efeac8595c09fed5a8e2e52b9adfee /src/southbridge | |
| parent | a4a9ad58ba685d5755a943c4a267c98a34f21599 (diff) | |
| download | coreboot-f4ed5dc7f47b465707170c2ad9bab11826dea12c.tar.xz | |
src/southbridge/amd: Remove unused variables
Change-Id: I143f3395a385e170cce0979707d6a7f61107f40b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/amd/common/amd_pci_util.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/southbridge/amd/common/amd_pci_util.c b/src/southbridge/amd/common/amd_pci_util.c index 103db988ef..f10a459bfd 100644 --- a/src/southbridge/amd/common/amd_pci_util.c +++ b/src/southbridge/amd/common/amd_pci_util.c @@ -100,7 +100,6 @@ void write_pci_cfg_irqs(void) u16 target_pin = 0; /* Pin we will search our tables for */ u16 int_line = 0; /* IRQ number read from PCI_INTR table and programmed to INT_LINE reg 0x3C */ u16 pci_intr_idx = 0; /* Index into PCI_INTR table, 0xC00/0xC01 */ - u8 bus = 0; /* A PCI Device Bus number */ u16 devfn = 0; /* A PCI Device and Function number */ u8 bridged_device = 0; /* This device is on a PCI bridge */ u32 i = 0; @@ -132,7 +131,6 @@ void write_pci_cfg_irqs(void) if (int_pin < 1 || int_pin > 4) continue; /* Device has invalid INT_PIN so skip it */ - bus = target_dev->bus->secondary; devfn = target_dev->path.pci.devfn; /* |