diff options
| author | Nico Huber <nico.h@gmx.de> | 2018-10-07 12:45:47 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-22 08:37:45 +0000 |
| commit | 3e1b3b1f4f48cfa3b2af28f44c0537ea19d0e8cb (patch) | |
| tree | 6e23f22489a1adc62b196f885b233b64cc8cfb44 /src/southbridge | |
| parent | 68dd00d634715d34f839985802d9dbf195db2bb3 (diff) | |
| download | coreboot-3e1b3b1f4f48cfa3b2af28f44c0537ea19d0e8cb.tar.xz | |
sb/amd/cimx/sb[89]00: Use CF9 reset
Implement board_reset() as "system reset".
Change-Id: I2d277b0845b4e8977b68892c2e5e00d8918e063f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29056
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/Kconfig | 3 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/reset.c | 19 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb900/Kconfig | 3 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb900/reset.c | 19 |
4 files changed, 12 insertions, 32 deletions
diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 07232f1a74..aa5160b68f 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -19,7 +19,8 @@ config SOUTHBRIDGE_AMD_CIMX_SB800 select IOAPIC select HAVE_USBDEBUG_OPTIONS select AMD_SB_CIMX - select HAVE_HARD_RESET + select HAVE_CF9_RESET + select HAVE_CF9_RESET_PREPARE if SOUTHBRIDGE_AMD_CIMX_SB800 config BOOTBLOCK_SOUTHBRIDGE_INIT diff --git a/src/southbridge/amd/cimx/sb800/reset.c b/src/southbridge/amd/cimx/sb800/reset.c index 40e861c215..b7ee613428 100644 --- a/src/southbridge/amd/cimx/sb800/reset.c +++ b/src/southbridge/amd/cimx/sb800/reset.c @@ -17,6 +17,7 @@ #define __SIMPLE_DEVICE__ #include <arch/io.h> +#include <cf9_reset.h> #include <reset.h> #define HT_INIT_CONTROL 0x6C @@ -24,7 +25,7 @@ #define NODE_PCI(x, fn) (((CONFIG_CDB+x)<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -static inline void set_bios_reset(void) +void cf9_reset_prepare(void) { u32 nodes; u32 htic; @@ -40,19 +41,7 @@ static inline void set_bios_reset(void) } } -void do_hard_reset(void) +void do_board_reset(void) { - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void do_soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); + system_reset(); } diff --git a/src/southbridge/amd/cimx/sb900/Kconfig b/src/southbridge/amd/cimx/sb900/Kconfig index 1fab6a7ec2..be3b16dd58 100644 --- a/src/southbridge/amd/cimx/sb900/Kconfig +++ b/src/southbridge/amd/cimx/sb900/Kconfig @@ -18,7 +18,8 @@ config SOUTHBRIDGE_AMD_CIMX_SB900 default n select IOAPIC select AMD_SB_CIMX - select HAVE_HARD_RESET + select HAVE_CF9_RESET + select HAVE_CF9_RESET_PREPARE if SOUTHBRIDGE_AMD_CIMX_SB900 config SATA_CONTROLLER_MODE diff --git a/src/southbridge/amd/cimx/sb900/reset.c b/src/southbridge/amd/cimx/sb900/reset.c index 40e861c215..b7ee613428 100644 --- a/src/southbridge/amd/cimx/sb900/reset.c +++ b/src/southbridge/amd/cimx/sb900/reset.c @@ -17,6 +17,7 @@ #define __SIMPLE_DEVICE__ #include <arch/io.h> +#include <cf9_reset.h> #include <reset.h> #define HT_INIT_CONTROL 0x6C @@ -24,7 +25,7 @@ #define NODE_PCI(x, fn) (((CONFIG_CDB+x)<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -static inline void set_bios_reset(void) +void cf9_reset_prepare(void) { u32 nodes; u32 htic; @@ -40,19 +41,7 @@ static inline void set_bios_reset(void) } } -void do_hard_reset(void) +void do_board_reset(void) { - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void do_soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); + system_reset(); } |