southbridge/amd/sb700: Set up uninitialized devices in early boot

LPC decodes were not enabled, leading to a failure of POST 80 cards
and similar debugging devices.  Enable the relevant LPC decodes
to allow debugging.

Additionally, the SMBUS controllers were not properly set up.
Enable both the primary and auxiliary controllers.

Finally, K10 and higher CPUs were hanging during boot due to
a misconfigued IOAPIC.  Properly configure the IOAPIC.

Change-Id: I9ffb6542ce445ac971fb81f4f554e7f1313e6a98
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12177
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)

4 files changed, 56 insertions, 8 deletions

diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c
index 67e6434de1..fb6f0888f8 100644
--- a/src/southbridge/amd/sb700/bootblock.c
+++ b/src/southbridge/amd/sb700/bootblock.c
@@ -1,6 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
+ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
  * Copyright (C) 2010 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -21,6 +22,9 @@
 #include <arch/io.h>
 #include <device/pci_ids.h>
 
+#define IO_MEM_PORT_DECODE_ENABLE_5	0x48
+#define IO_MEM_PORT_DECODE_ENABLE_6	0x4a
+
 /*
  * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
  *
@@ -35,14 +39,21 @@
 static void sb700_enable_rom(void)
 {
 	u8 reg8;
+	u32 dword;
 	pci_devfn_t dev;
 
 	dev = PCI_DEV(0, 0x14, 3);
 
+	/* The LPC settings below work for SPI flash as well;
+	 * the hardware does not distinguish between LPC and SPI flash ROM
+	 * aside from offering additional side-channel access to SPI flash
+	 * via a separate register-based interface.
+	 */
+
 	/* Decode variable LPC ROM address ranges 1 and 2. */
-	reg8 = pci_io_read_config8(dev, 0x48);
+	reg8 = pci_io_read_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5);
 	reg8 |= (1 << 3) | (1 << 4);
-	pci_io_write_config8(dev, 0x48, reg8);
+	pci_io_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5, reg8);
 
 	/* LPC ROM address range 1: */
 	/* Enable LPC ROM range mirroring start at 0x000e(0000). */
@@ -57,10 +68,32 @@ static void sb700_enable_rom(void)
 	 * 0xfff0(0000): 1MB
 	 * 0xffe0(0000): 2MB
 	 * 0xffc0(0000): 4MB
+	 * 0xff80(0000): 8MB
 	 */
 	pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
 	/* Enable LPC ROM range end at 0xffff(ffff). */
 	pci_io_write_config16(dev, 0x6e, 0xffff);
+
+	/* SB700 LPC Bridge 0x48.
+	 * Turn on all LPC IO Port decode enables
+	 */
+	pci_io_write_config32(dev, 0x44, 0xffffffff);
+
+	/* SB700 LPC Bridge 0x48.
+	 * BIT0: Port Enable for SuperIO 0x2E-0x2F
+	 * BIT1: Port Enable for SuperIO 0x4E-0x4F
+	 * BIT6: Port Enable for RTC IO 0x70-0x73
+	 */
+	reg8 = pci_io_read_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5);
+	reg8 |= (1 << 0) | (1 << 1) | (1 << 6);
+	pci_io_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5, reg8);
+
+	/* SB700 LPC Bridge 0x4a.
+	 * BIT5: Port Enable for Port 0x80
+	 */
+	reg8 = pci_io_read_config8(dev, IO_MEM_PORT_DECODE_ENABLE_6);
+	reg8 |= (1 << 5);
+	pci_io_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_6, reg8);
 }
 
 static void bootblock_southbridge_init(void)
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index 2828bbed51..8ab97adce1 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -395,6 +396,15 @@ static void sb700_devices_por_init(void)
 	byte |= (1 << 0);
 	pci_write_config8(dev, 0xd2, byte);
 
+	/* set auxiliary smbus iobase and enable controller */
+	pci_write_config32(dev, 0x58, SMBUS_AUX_IO_BASE | 1);
+
+	if (inb(SMBUS_IO_BASE) == 0xff)
+		printk(BIOS_INFO, "%s: Primary SMBUS controller I/O not found\n", __func__);
+
+	if (inb(SMBUS_AUX_IO_BASE) == 0xff)
+		printk(BIOS_INFO, "%s: Secondary SMBUS controller I/O not found\n", __func__);
+
 	/* KB2RstEnable */
 	pci_write_config8(dev, 0x40, 0x44);
 
diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c
index a39ec1849e..0cc1e8bd3c 100644
--- a/src/southbridge/amd/sb700/lpc.c
+++ b/src/southbridge/amd/sb700/lpc.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -45,6 +46,8 @@ static void lpc_init(device_t dev)
 	u32 dword;
 	device_t sm_dev;
 
+	printk(BIOS_SPEW, "%s\n", __func__);
+
 	/* Enable the LPC Controller */
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
 	dword = pci_read_config32(sm_dev, 0x64);
diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c
index 16958a2620..83a722bcb2 100644
--- a/src/southbridge/amd/sb700/sm.c
+++ b/src/southbridge/amd/sb700/sm.c
@@ -62,11 +62,9 @@ static void sm_init(device_t dev)
 	printk(BIOS_INFO, "sm_init().\n");
 
 	rev = get_sb700_revision(dev);
-	ioapic_base = (void *)(pci_read_config32(dev, 0x74) & (0xffffffe0));	/* some like mem resource, but does not have  enable bit */
-	/* Don't rename APIC ID */
-	/* TODO: We should call setup_ioapic() here. But kernel hangs if cpu is K8.
-	 * We need to check out why and change back. */
-	clear_ioapic(ioapic_base);
+	/* This works in a similar fashion to a memory resource, but without an enable bit */
+	ioapic_base = (void *)(pci_read_config32(dev, 0x74) & (0xffffffe0));
+	setup_ioapic(ioapic_base, 0); /* Don't rename IOAPIC ID. */
 
 	/* 2.10 Interrupt Routing/Filtering */
 	dword = pci_read_config8(dev, 0x62);
@@ -298,6 +296,10 @@ static void sm_init(device_t dev)
 	byte &= ~(1 << 1);
 	pm_iowrite(0x59, byte);
 
+	/* Enable SCI as irq9. */
+	outb(0x4, 0xC00);
+	outb(0x9, 0xC01);
+
 	printk(BIOS_INFO, "sm_init() end\n");
 
 	/* Enable NbSb virtual channel */
@@ -388,7 +390,7 @@ static void sb700_sm_read_resources(device_t dev)
 	struct resource *res;
 
 	/* Get the normal pci resources of this device */
-	/* pci_dev_read_resources(dev); */
+	pci_dev_read_resources(dev);
 
 	/* apic */
 	res = new_resource(dev, 0x74);